The following series includes emulation of the platform-specific MIPS extension for Cavium Octeon CPUS: - basic Octeon vCPU model - custom instruction decoder for Octeon - implementation of arithmetic and logic instructions
--- Pavel Dovgalyuk (3): target/mips: introduce generic Cavium Octeon CPU model target/mips: implement Octeon-specific BBIT instructions target/mips: implement Octeon-specific arithmetic instructions target/mips/helper.h | 1 + target/mips/tcg/meson.build | 3 + target/mips/tcg/octeon.decode | 39 +++++ target/mips/tcg/octeon_helper.c | 22 +++ target/mips/tcg/octeon_helper.h.inc | 10 ++ target/mips/tcg/octeon_translate.c | 235 ++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 5 + target/mips/tcg/translate.h | 1 + 8 files changed, 316 insertions(+) create mode 100644 target/mips/tcg/octeon.decode create mode 100644 target/mips/tcg/octeon_helper.c create mode 100644 target/mips/tcg/octeon_helper.h.inc create mode 100644 target/mips/tcg/octeon_translate.c -- Pavel Dovgalyuk