On Tue, 7 Jun 2022 at 21:36, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This includes the build rules for the decoder, and the
> new file for translation, but excludes any instructions.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/translate-a64.h | 1 +
> target/arm/translate-a64.c | 7 ++++++-
> target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++
> target/arm/meson.build | 2 ++
> target/arm/sme.decode | 20 ++++++++++++++++++++
> 5 files changed, 64 insertions(+), 1 deletion(-)
> create mode 100644 target/arm/translate-sme.c
> create mode 100644 target/arm/sme.decode
>
> diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
> index f0970c6b8c..789b6e8e78 100644
> --- a/target/arm/translate-a64.h
> +++ b/target/arm/translate-a64.h
> @@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s)
> }
>
> bool disas_sve(DisasContext *, uint32_t);
> +bool disas_sme(DisasContext *, uint32_t);
>
> void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
> uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index b1d2840819..8a38fbc33b 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -14814,7 +14814,12 @@ static void
> aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> }
>
> switch (extract32(insn, 25, 4)) {
> - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
> + case 0x0:
> + if (!disas_sme(s, insn)) {
> + unallocated_encoding(s);
> + }
> + break;
I still think we should check bit 31 here.
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
