From: Dragan Mladjenovic <dragan.mladjeno...@syrmia.com>
nanoMIPS ISA does not support unaligned memory access. Adjust
DisasContext's default_tcg_memop_mask to reflect this.
Signed-off-by: Dragan Mladjenovic <dragan.mladjeno...@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pe...@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-Id: <20220504110403.613168-6-stefan.pe...@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/tcg/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6de5b66650..5f460fb687 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16023,8 +16023,9 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
- INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
+ ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&
+ (ctx->insn_flags & (ISA_MIPS_R6 |
+ INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;
/*
* Execute a branch and its delay slot as a single instruction.
--
2.36.1
