On 2022/7/4 下午1:18, Richard Henderson wrote:
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Is it a typo in the manual that says "2VS", i.e. multiplication?
Is '2^VS', the manual is wrong.
Thanks.
Song Gao
If so,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
Signed-off-by: Xiaojuan Yang <yangxiaoj...@loongson.cn>
---
target/loongarch/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 4c8f96bc3a..04e5e47da4 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -219,6 +219,10 @@ static void loongarch_cpu_do_interrupt(CPUState
*cs)
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
+ if (vec_size) {
+ vec_size = (1 << vec_size) * 4;
+ }
+
if (cs->exception_index == EXCCODE_INT) {
/* Interrupt */
uint32_t vector = 0;
