On 7/1/22 16:36, Peter Maydell wrote:
+ /*
+ * The SME exception we are testing for is raised via
+ * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called
+ * when EL1 is using A64 or EL2 using A64 and !TGE.
+ * See AArch32.CheckAdvSIMDOrFPEnabled().
+ */
+ if (el == 0
+ && FIELD_EX64(env->svcr, SVCR, SM)
+ && (!arm_is_el2_enabled(env)
+ || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
+ && arm_el_is_aa64(env, 1)
+ && !sme_fa64(env, el)) {
I can't get any of:
* the logic in the comment
* the logic in the C code
* the logic in the the pseudocode AArch32.CheckAdvSIMDOrFPEnabled()
which causes it to call AArch64.CheckFPEnabled()
to line up with each other.
The comment has:
* (EL1 A64) OR (EL2 A64 && !TGE)
The pseudocode has:
* (!TGE && EL1 A64) OR (TGE && EL2 A64 && EL1 A64)
[seems odd that it is checking the width of EL1 in the TGE case
but I haven't followed the logic through to find out why]
The C code here has:
* (!TGE && EL2 A64 && EL1 A64)
What am I missing ?
I'm looking at 0487H.a... are you looking at a different version?
Because the pseudocode I see isn't what you list above:
if PSTATE.EL == EL0 && (!EL2Enabled() || (!ELUsingAArch32(EL2) && HCR_EL2.TGE == '0'))
&&
!ELUsingAArch32(EL1) then
So
(!EL2 || (EL2 A64 && !TGE)) && EL1 A64
which is, as far as I can see, what the C code has.
I'll adjust the comment, anyway.
r~