Re: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations

[Alistair Francis]

On Sun, Jul 10, 2022 at 6:25 PM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> - There are 3 suggested privilege modes conbinations listed in the spec:
> 1) M, 2) M, U 3) M, S, U
>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bb3973806..0dad6906bc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -636,6 +636,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>              return;
>          }
>
> +        if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
> +            error_setg(errp,
> +                       "Setting S extension without U extension is illegal");
> +            return;
> +        }
> +
>          if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
>              error_setg(errp, "F extension requires Zicsr");
>              return;
> --
> 2.17.1
>
>