From: Tobias Röhmel <quic_troh...@quicinc.com> Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the Cortex-R52 MPU which uses and combines cache attributes of different translation levels.
Signed-off-by: Tobias Röhmel <quic_troh...@quicinc.com> --- target/arm/internals.h | 13 +++++++------ target/arm/m_helper.c | 3 ++- target/arm/ptw.c | 11 +++++++---- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6f94f3019d..b03049d920 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1109,12 +1109,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, V8M_SAttributes *sattrs); -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); - /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { /* @@ -1126,6 +1120,13 @@ typedef struct ARMCacheAttrs { bool is_s2_format:1; } ARMCacheAttrs; +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion, + ARMCacheAttrs *cacheattrs); + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index a740c3e160..44c80d733a 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2829,10 +2829,11 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) != 0 || alt) { + ARMCacheAttrs cacheattrs = {0}; /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, &attrs, &prot, &is_subpage, - &fi, &mregion); + &fi, &mregion, &cacheattrs); if (mregion == -1) { mrvalid = false; mregion = 0; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b037c1f55..c4f5721012 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1702,7 +1702,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) + ARMMMUFaultInfo *fi, uint32_t *mregion, + ARMCacheAttrs *cacheattrs) { /* * Perform a PMSAv8 MPU lookup (without also doing the SAU check @@ -1968,7 +1969,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi) + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { uint32_t secure = regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs = {}; @@ -2036,7 +2037,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, } ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, &mpu_is_subpage, fi, NULL); + txattrs, prot, &mpu_is_subpage, fi, + NULL, cacheattrs); *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; } @@ -2416,7 +2418,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, -- 2.25.1