On Mon, Jul 25, 2022 at 1:48 PM Dao Lu <da...@rivosinc.com> wrote: > > This patch adds RISC-V Zihintpause support. The extension is set to be enabled > by default and opcode has been added to insn32.decode. > > Added trans_pause to exit the TB and return to main loop. > > The change can also be found in: > https://github.com/dlu42/qemu/tree/zihintpause_support_v1 > > Tested along with pause support added to cpu_relax function for linux, the > changes I made to linux to test can be found here: > https://github.com/dlu42/linux/tree/pause_support_v1 > > -------- > Changelog: > > v1 -> v2 > 1. Pause now also exit the TB and return to main loop > 2. Move the REQUIRE_ZIHINTPAUSE macro inside the trans_pause function > > v2 -> v3 > No changes, v2 was lost from the list > > v3 -> v4 > No longer break the reservation in trans_pause > > v4 -> v5 > Rabase on top of https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > Dao Lu (1): > Add Zihintpause support
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 7 ++++++- > target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++++ > 4 files changed, 25 insertions(+), 1 deletion(-) > > -- > 2.25.1 > >