On Thu, Aug 11, 2022 at 5:02 AM Atish Patra <ati...@rivosinc.com> wrote: > > This series implements Sstc extension[1] which was ratified recently. > > The first patch is a prepartory patches while PATCH 2 adds stimecmp > support while PATCH 3 adds vstimecmp support. This series is based on > on top of upstream commit (faee5441a038). > > The series can also be found at > https://github.com/atishp04/qemu/tree/sstc_v9 > > It is tested on RV32 & RV64 with latest OpenSBI & Linux kernel[2] > patches. > > Changes from v8->v9: > 1. Updated alignment of few lines. > 2. Improved predicate functions for sstc. > > Changes from v7->v8: > 1. Removed redundant blank lines. > 2. Invoke smode & hmode predicate function from sstc related predicate > functions. > > Changes from v6->v7: > 1. Replaced g_malloc0 with g_new0. > 2. Removed the over allocation for the timers. > > Changes from v5->v6: > 1. Rebased on top of the latest HEAD commit. > > Changes from v4->v5: > 1. Removed any ordering related flags and emulate the hardware more > closely. > > Changes from v3->v4: > 1. Added [v]stimecmp_wr_done to the corresponding vmstate strucuture. > > Changes from v2->v3: > 1. Dropped generic migration code improvement patches. > 2. Removed the order constraints while updating stimecmp/vstimecmp. > > Changes from v1->v2: > 1. Rebased on the latest upstream commit. > 2. Replaced PATCH 1 with another patch where mtimer/timecmp is > moved from CPU to ACLINT. > 3. Added ACLINT migration support. > > [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view > [2] https://github.com/atishp04/linux/tree/sstc_v8 > > Atish Patra (3): > hw/intc: Move mtimer/mtimecmp to aclint > target/riscv: Add stimecmp support > target/riscv: Add vstimecmp support
Thanks! Applied to riscv-to-apply.next Alistair > > hw/intc/riscv_aclint.c | 41 +++++--- > hw/timer/ibex_timer.c | 18 ++-- > include/hw/intc/riscv_aclint.h | 2 + > include/hw/timer/ibex_timer.h | 2 + > target/riscv/cpu.c | 9 ++ > target/riscv/cpu.h | 11 ++- > target/riscv/cpu_bits.h | 8 ++ > target/riscv/cpu_helper.c | 11 ++- > target/riscv/csr.c | 168 +++++++++++++++++++++++++++++++++ > target/riscv/machine.c | 7 +- > target/riscv/meson.build | 3 +- > target/riscv/time_helper.c | 114 ++++++++++++++++++++++ > target/riscv/time_helper.h | 30 ++++++ > 13 files changed, 392 insertions(+), 32 deletions(-) > create mode 100644 target/riscv/time_helper.c > create mode 100644 target/riscv/time_helper.h > > -- > 2.25.1 > >