From: Christoph Müllner <christoph.muell...@vrull.eu> This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910 processors: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync
The xthead* extensions are documented here: https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf The "th." instruction prefix prevents future conflicts with standard extensions and has been documentented in a PR for the RISC-V toolchain conventions: https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 The goal of this patchset is to provide access to these instruction so that compilers/users can optimize SW accordingly. Note, that the T-Head vendor extensions do not contain all vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are included). Instead the extensions cover coherent functionality, that is exposed to S and U mode. To enable the extensions above, the following two methods are possible: * add the extension to the arch string (e.g. * QEMU_CPU="any,xtheadcmo=true,xtheadsync=true") * implicitly select the extensions via CPU selection (e.g. * QEMU_CPU="thead-c910") This patchset attempts to minimize code changes in generic/infrastructure code. This patchset allows to boot the Xuantie Linux kernel. Christoph Müllner (11): riscv: Add privilege level to DisasContext RISC-V: Adding T-Head CMO instructions RISC-V: Adding T-Head SYNC instructions RISC-V: Adding T-Head Bitmanip instructions RISC-V: Adding T-Head CondMov instructions RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding T-Head XMAE support RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head FMemIdx extension RISC-V: Add initial support for T-Head C906 and C910 CPUs target/riscv/cpu.c | 43 + target/riscv/cpu.h | 14 + target/riscv/cpu_helper.c | 6 +- target/riscv/cpu_vendorid.h | 6 + target/riscv/insn_trans/trans_xthead.c.inc | 874 +++++++++++++++++++++ target/riscv/meson.build | 10 + target/riscv/translate.c | 42 +- target/riscv/xtheadba.decode | 46 ++ target/riscv/xtheadbb.decode | 62 ++ target/riscv/xtheadbs.decode | 32 + target/riscv/xtheadcmo.decode | 43 + target/riscv/xtheadcondmov.decode | 33 + target/riscv/xtheadfmemidx.decode | 34 + target/riscv/xtheadmac.decode | 30 + target/riscv/xtheadmemidx.decode | 73 ++ target/riscv/xtheadmempair.decode | 29 + target/riscv/xtheadsync.decode | 25 + 17 files changed, 1397 insertions(+), 5 deletions(-) create mode 100644 target/riscv/cpu_vendorid.h create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xtheadba.decode create mode 100644 target/riscv/xtheadbb.decode create mode 100644 target/riscv/xtheadbs.decode create mode 100644 target/riscv/xtheadcmo.decode create mode 100644 target/riscv/xtheadcondmov.decode create mode 100644 target/riscv/xtheadfmemidx.decode create mode 100644 target/riscv/xtheadmac.decode create mode 100644 target/riscv/xtheadmemidx.decode create mode 100644 target/riscv/xtheadmempair.decode create mode 100644 target/riscv/xtheadsync.decode -- 2.37.2