On Tue, 6 Sept 2022 at 19:23, Alex Bennée <alex.ben...@linaro.org> wrote: > > QEMU doesn't model micro-architectural details which includes most > chip errata. The ARM_ERRATA_798181 work around in the Linux > kernel (see erratum_a15_798181_init) currently detects QEMU's > cortex-a15 as broken and triggers additional expensive TLB flushes as > a result. > > Change the MIDR to report what the latest silicon would (r4p0) as well > as setting the IMPDEF revidr bit to indicate these flushes are not > needed. This cuts about 5s from my Debian kernel boot with the latest > 6.0rc1 kernel (29s->24s). > > Signed-off-by: Alex Bennée <alex.ben...@linaro.org> > Cc: Arnd Bergmann <a...@linaro.org> > Cc: Anders Roxell <anders.rox...@linaro.org>
Tested-by: Anders Roxell <anders.rox...@linaro.org> > --- > target/arm/cpu_tcg.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c > index 3099b38e32..59d5278868 100644 > --- a/target/arm/cpu_tcg.c > +++ b/target/arm/cpu_tcg.c > @@ -588,7 +588,9 @@ static void cortex_a15_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_EL3); > set_feature(&cpu->env, ARM_FEATURE_PMU); > cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; > - cpu->midr = 0x412fc0f1; > + /* r4p0 cpu, not requiring expensive tlb flush errata */ > + cpu->midr = 0x414fc0f0; > + cpu->revidr = 0x200; > cpu->reset_fpsid = 0x410430f0; > cpu->isar.mvfr0 = 0x10110222; > cpu->isar.mvfr1 = 0x11111111; > -- > 2.34.1 >