On Thu, Sep 15, 2022 at 11:29 PM Bernhard Beschow <shen...@gmail.com> wrote: > > Models the real device more closely.
Please describe the source (e.g.: I assume it's MPC8544DS board manual or something like that?) that describe such memory map for the platform bus. Is this the eLBC bus range that includes the NOR flash device? > > Signed-off-by: Bernhard Beschow <shen...@gmail.com> > --- > hw/ppc/mpc8544ds.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c > index 81177505f0..cd6cd04bef 100644 > --- a/hw/ppc/mpc8544ds.c > +++ b/hw/ppc/mpc8544ds.c > @@ -14,6 +14,7 @@ > #include "sysemu/device_tree.h" > #include "hw/ppc/openpic.h" > #include "qemu/error-report.h" > +#include "qemu/units.h" > #include "cpu.h" > > static void mpc8544ds_fixup_devtree(void *fdt) > @@ -45,6 +46,11 @@ static void e500plat_machine_class_init(ObjectClass *oc, > void *data) > pmc->pci_nr_slots = 2; > pmc->fixup_devtree = mpc8544ds_fixup_devtree; > pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; > + pmc->has_platform_bus = true; > + pmc->platform_bus_base = 0xEC000000ULL; > + pmc->platform_bus_size = 128 * MiB; > + pmc->platform_bus_first_irq = 5; > + pmc->platform_bus_num_irqs = 10; > pmc->ccsrbar_base = 0xE0000000ULL; > pmc->pci_mmio_base = 0xC0000000ULL; > pmc->pci_mmio_bus_base = 0xC0000000ULL; > -- Regards, Bin