Nothing special going on here, for once.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 5 +++
target/i386/tcg/emit.c.inc | 75 ++++++++++++++++++++++++++++++++
target/i386/tcg/translate.c | 1 +
3 files changed, 81 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 798b423163..461921a98d 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -648,6 +648,11 @@ static const X86OpEntry opcodes_0F[256] = {
[0x7e] = X86_OP_GROUP0(0F7E),
[0x7f] = X86_OP_GROUP0(0F7F),
+ [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3
p_00_66_f3_f2),
+ [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
+ [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
+ [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
+
[0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3)
p_66_f2),
[0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
[0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index dd36a3544e..71b8fcbe24 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1342,6 +1342,11 @@ static void gen_PINSRB(DisasContext *s, CPUX86State
*env, X86DecodedInsn *decode
gen_pinsr(s, env, decode, MO_8);
}
+static void gen_PINSRW(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
+{
+ gen_pinsr(s, env, decode, MO_16);
+}
+
static void gen_PINSR(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
{
gen_pinsr(s, env, decode, decode->op[2].ot);
@@ -1648,6 +1653,66 @@ static void gen_VAESIMC(DisasContext *s, CPUX86State
*env, X86DecodedInsn *decod
gen_helper_aesimc_xmm(cpu_env, OP_PTR0, OP_PTR2);
}
+/*
+ * 00 = v*ps Vps, Hps, Wpd
+ * 66 = v*pd Vpd, Hpd, Wps
+ * f3 = v*ss Vss, Hss, Wps
+ * f2 = v*sd Vsd, Hsd, Wps
+ */
+#define SSE_CMP(x) { \
+ gen_helper_ ## x ## ps ## _xmm, gen_helper_ ## x ## pd ## _xmm, \
+ gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, \
+ gen_helper_ ## x ## ps ## _ymm, gen_helper_ ## x ## pd ## _ymm}
+static const SSEFunc_0_eppp gen_helper_cmp_funcs[32][6] = {
+ SSE_CMP(cmpeq),
+ SSE_CMP(cmplt),
+ SSE_CMP(cmple),
+ SSE_CMP(cmpunord),
+ SSE_CMP(cmpneq),
+ SSE_CMP(cmpnlt),
+ SSE_CMP(cmpnle),
+ SSE_CMP(cmpord),
+
+ SSE_CMP(cmpequ),
+ SSE_CMP(cmpnge),
+ SSE_CMP(cmpngt),
+ SSE_CMP(cmpfalse),
+ SSE_CMP(cmpnequ),
+ SSE_CMP(cmpge),
+ SSE_CMP(cmpgt),
+ SSE_CMP(cmptrue),
+
+ SSE_CMP(cmpeqs),
+ SSE_CMP(cmpltq),
+ SSE_CMP(cmpleq),
+ SSE_CMP(cmpunords),
+ SSE_CMP(cmpneqq),
+ SSE_CMP(cmpnltq),
+ SSE_CMP(cmpnleq),
+ SSE_CMP(cmpords),
+
+ SSE_CMP(cmpequs),
+ SSE_CMP(cmpngeq),
+ SSE_CMP(cmpngtq),
+ SSE_CMP(cmpfalses),
+ SSE_CMP(cmpnequs),
+ SSE_CMP(cmpgeq),
+ SSE_CMP(cmpgtq),
+ SSE_CMP(cmptrues),
+};
+#undef SSE_CMP
+
+static void gen_VCMP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
+{
+ int index = decode->immediate & (s->prefix & PREFIX_VEX ? 31 : 7);
+ int b =
+ s->prefix & PREFIX_REPZ ? 2 /* ss */ :
+ s->prefix & PREFIX_REPNZ ? 3 /* sd */ :
+ !!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2);
+
+ gen_helper_cmp_funcs[index][b](cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+}
+
static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
{
gen_unary_fp_sse(s, env, decode,
@@ -1793,6 +1858,16 @@ static void gen_VROUNDSS(DisasContext *s, CPUX86State
*env, X86DecodedInsn *deco
gen_helper_roundss_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
}
+static void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
+{
+ TCGv_i32 imm = tcg_constant_i32(decode->immediate);
+ SSEFunc_0_pppi ps, pd, fn;
+ ps = s->vex_l ? gen_helper_shufps_ymm : gen_helper_shufps_xmm;
+ pd = s->vex_l ? gen_helper_shufpd_ymm : gen_helper_shufpd_xmm;
+ fn = s->prefix & PREFIX_DATA ? pd : ps;
+ fn(OP_PTR0, OP_PTR1, OP_PTR2, imm);
+}
+
static void gen_VZEROALL(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
{
TCGv_ptr ptr = tcg_temp_new_ptr();
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 32f937013f..eb7a4d0e4d 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4697,6 +4697,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
if (use_new &&
(b == 0x138 || b == 0x13a ||
(b >= 0x150 && b <= 0x17f) ||
+ b == 0x1c2 || (b >= 0x1c4 && b <= 0x1c6) ||
(b >= 0x1d0 && b <= 0x1ff))) {
disas_insn_new(s, cpu, b + 0x100);
return s->pc;
--
2.37.2
