On 9/24/22 14:28, BALATON Zoltan wrote:
These are used by both the SDRAM controller model and system DCRs. In
preparation to move SDRAM controller in its own file move these macros
to the ppc4xx.h header.

Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>

Reviewed-by: Cédric Le Goater <c...@kaod.org>

Thanks,

C.


---
  hw/ppc/ppc440_uc.c      | 4 ----
  include/hw/ppc/ppc4xx.h | 4 ++++
  2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 46daecab19..0a41274d63 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -380,10 +380,6 @@ enum {
      PESDR1_RSTSTA = 0x365,
  };
-#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
-#define SDR0_DDR0_DDRM_DDR1       0x20000000
-#define SDR0_DDR0_DDRM_DDR2       0x40000000
-
  static uint32_t dcr_read_sdr(void *opaque, int dcrn)
  {
      ppc4xx_sdr_t *sdr = opaque;
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index ff88385ac0..10c6dd535f 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -111,6 +111,10 @@ struct Ppc4xxEbcState {
  };
/* SDRAM DDR controller */
+#define SDR0_DDR0_DDRM_ENCODE(n)  ((((unsigned long)(n)) & 0x03) << 29)
+#define SDR0_DDR0_DDRM_DDR1       0x20000000
+#define SDR0_DDR0_DDRM_DDR2       0x40000000
+
  #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
  OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
  struct Ppc4xxSdramDdrState {


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