From: Alistair Francis <alistair.fran...@wdc.com> The following changes since commit 99d6b11b5b44d7dd64f4cb1973184e40a4a174f8:
Merge tag 'pull-target-arm-20220922' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-09-26 13:38:26 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20220927 for you to fetch changes up to a3ab69f9f6c000481c439923d16416b8941d5b37: target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered (2022-09-27 11:23:57 +1000) ---------------------------------------------------------------- Second RISC-V PR for QEMU 7.2 * Fixup typos and register addresses for Ibex SPI * Cleanup the RISC-V virt machine documentation * Remove the sideleg and sedeleg CSR macros * Fix the CSR check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} * Remove fixed numbering from GDB xml feature files * Allow setting the resetvec for the OpenTitan machine * Check the correct exception cause in vector GDB stub * Fix inheritance of SiFiveEState * Improvements to the RISC-V debugger spec * Simplify some vector code ---------------------------------------------------------------- Alex Bennée (1): docs/system: clean up code escape for riscv virt platform Alistair Francis (3): target/riscv: Set the CPU resetvec directly hw/riscv: opentitan: Fixup resetvec hw/riscv: opentitan: Expose the resetvec as a SoC property Andrew Burgess (2): target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml target/riscv: remove fixed numbering from GDB xml feature files Bernhard Beschow (1): hw/riscv/sifive_e: Fix inheritance of SiFiveEState Frank Chang (9): target/riscv: Check the correct exception cause in vector GDB stub target/riscv: debug: Determine the trigger type from tdata1.type target/riscv: debug: Introduce build_tdata1() to build tdata1 register content target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs target/riscv: debug: Restrict the range of tselect value can be written target/riscv: debug: Introduce tinfo CSR target/riscv: debug: Create common trigger actions function target/riscv: debug: Check VU/VS modes for type 2 trigger target/riscv: debug: Add initial support of type 6 trigger Rahul Pathak (1): target/riscv: Remove sideleg and sedeleg Weiwei Li (1): target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Wilfred Mallawa (2): hw/ssi: ibex_spi: fixup typos in ibex_spi_host hw/ssi: ibex_spi: update reg addr Yang Liu (2): target/riscv: rvv-1.0: Simplify vfwredsum code target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered docs/system/riscv/virt.rst | 13 +- include/hw/riscv/opentitan.h | 2 + include/hw/riscv/sifive_e.h | 3 +- target/riscv/cpu.h | 9 +- target/riscv/cpu_bits.h | 3 +- target/riscv/debug.h | 55 ++-- target/riscv/helper.h | 15 +- target/riscv/insn32.decode | 6 +- disas/riscv.c | 2 - hw/riscv/opentitan.c | 8 +- hw/ssi/ibex_spi_host.c | 8 +- target/riscv/cpu.c | 13 +- target/riscv/csr.c | 23 +- target/riscv/debug.c | 484 +++++++++++++++++++++++++------- target/riscv/gdbstub.c | 36 +-- target/riscv/machine.c | 26 +- target/riscv/vector_helper.c | 69 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 6 +- gdb-xml/riscv-32bit-cpu.xml | 6 +- gdb-xml/riscv-32bit-fpu.xml | 10 +- gdb-xml/riscv-64bit-cpu.xml | 6 +- gdb-xml/riscv-64bit-fpu.xml | 10 +- 22 files changed, 531 insertions(+), 282 deletions(-)
