On Fri, Oct 07, 2022 at 11:16:19AM -0700, Davidlohr Bueso wrote: > > Yeah, putting this back together was on my todo list, but happy to see > patches are out. Recollecting my thoughts on this, my original approach > was also to support only volatile or persistent capacities, but through > two backends, and thus two address spaces. Afaik the last idea that was > discussed on IRC in this regard was to do it with a single backend along > with a pmem_offset=N boundary (0 or 100% for example for one type or the > other) tunnable. >
This makes sense. References another message I sent, are the region areas in the dvsecs an artifact from cxl1.x? They suggest only two regions are supported. Was this overridden by the introduction of CDAT fields that describe the memory layout? (sorry, just trying to put together the puzzle pieces here, jumping in a bit late to the party). > > > > > > Example command lines > > > > > > --------------------- > > > > > > -A very simple setup with just one directly attached CXL Type 3 > > > > > > device:: > > > > > > +A very simple setup with just one directly attached CXL Type 3 > > > > > > Persistent Memory device:: > > > > > > > > > > > > qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m > > > > > > 4g,maxmem=8G,slots=8 -cpu max \ > > > > > > ... > > > > > > @@ -308,7 +308,18 @@ A very simple setup with just one directly > > > > > > attached CXL Type 3 device:: > > > > > > -object > > > > > > memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M > > > > > > \ > > > > > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > > > > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > > > > > - -device > > > > > > cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 > > > > > > \ > > > > > > + -device > > > > > > cxl-type3,bus=root_port13,pmem=true,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 > > > > > > \ > > So regardless of the interface we end up with, volatile and lsa parameters > should be mutually exclusive. > Spec says that volatile devices `may` implement an lsa. Get LSA (Opcode 4102h) The Label Storage Area (LSA) shall be supported by a memory device that provides persistent memory capacity and may be supported by a device that provides only volatile memory capacity. The format of the LSA is specified in Section 9.13.2. The size of the Label Storage Area is retrieved from the Identify Memory Device command.
