On Tue, 18 Oct 2022 14:26:41 -0700 "Viacheslav A.Dubeyko" <viacheslav.dube...@bytedance.com> wrote:
> Hi Jonathan, > > > On Oct 13, 2022, at 8:09 AM, Jonathan Cameron <jonathan.came...@huawei.com> > > wrote: > > > > <skipped> > > >> So, I would like to contribute to QEMU emulation of CXL memory > >> support. And I would like to see a TODO list. I hope this list could > >> be useful not only for me. As far as I can see, we can summarize: > > > > Absolutely agree on need for a TODO now there are multiple groups involved > > As far as I can see, Fabric Management looks like “uncharted territory” with > a lot of work. I think it’s pretty interesting direction for me to start. > I can read Compute Express Link Specification (Revision 3.0, Version 1.0). > Could you recommend some other docs or links to take a look? So far the spec is all I'm aware of at the level of actually talking to the hardware. Probably some wooly presentations on what people 'might build'. There are some other efforts that may be related to higher level - e.g. what talks to the FM that then talks to the CXL devices. I've not looked into them but google feeds me: https://www.dmtf.org/documents/redfish-spmf/redfish-cxl-device-management-models-bundle-08wip https://www.dmtf.org/content/dmtf-and-cxl-consortium-establish-work-register One interesting diversion in this space would be to get the MCTP interfaces up and running (perhaps via i2c). The last time I looked at that, the issue was that there wasn't any overlap between suitable I2C controllers (need to support master and subordinate roles) and ones with ACPI bindings. Doing it over PCIe VDMs is also an option. The interest here would be to put a second transport option in place so that any userspace FM code would work well with that and via the mailbox interfaces. Early work on the i2c approach at: https://lore.kernel.org/qemu-devel/20220520165909.4369-1-jonathan.came...@huawei.com/ For now I've abandoned that as CXL 3.0 got published with the Switch mailbox path (+ support for tunneling commands via a normal mailbox on multi head devices). > > By the way, I see ARM64 support in TODO list. But nothing related to RISC-V. > Do we need to consider RISC-V too? I'm only going to focus on architectures I have reason to support - there's enough work to keep me busy without adding more! More than happy to review / comment on support for risc-v though. The same applies to Power (no idea on IBM's plans, but they are a BoD level member of CXL so I assume they may have some.) Jonathan > > Thanks, > Slava. > > >
