Taylor Simpson <tsimp...@quicinc.com> wrote:
>
> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
> index eae358cf33..e60dbf0e7a 100644
> --- a/target/hexagon/translate.h
> +++ b/target/hexagon/translate.h
> @@ -54,6 +54,9 @@ typedef struct DisasContext {
> bool qreg_is_predicated[NUM_QREGS];
> int qreg_log_idx;
> bool pre_commit;
> + bool has_single_direct_branch;
> + TCGv branch_cond;
> + target_ulong branch_dest;
> } DisasContext;
>
> static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
> diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
> index fba76d3b38..07b4326e56 100644
> --- a/target/hexagon/genptr.c
> +++ b/target/hexagon/genptr.c
> @@ -505,15 +505,14 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx,
> Packet *pkt,
> gen_set_label(pred_false);
> }
> } else {
> - TCGLabel *pred_false = NULL;
> + /* Defer this jump to the end of the TB */
> + g_assert(ctx->branch_cond == NULL);
> + ctx->has_single_direct_branch = true;
> if (pred != NULL) {
> - pred_false = gen_new_label();
> - tcg_gen_brcondi_tl(TCG_COND_EQ, pred, 0, pred_false);
> - }
> - tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
> - if (pred != NULL) {
> - gen_set_label(pred_false);
> + ctx->branch_cond = tcg_temp_local_new();
> + tcg_gen_mov_tl(ctx->branch_cond, pred);
> }
> + ctx->branch_dest = dest;
> }
> }
Do we want to perform this logic at gen_write_new_pc_addr() as well?
Although, in that case, we would need a separate ctx->branch_dest to
hold a TCGv instead of target_ulong...
Or have a single variable (TCGv) but add an extra
tcg_gen_addi(ctx->branch_dest, tcg_gen_constant_tl(pkt->pc), pc_off)
call to gen_write_new_pc_pcrel(). (In which case, we could also
unify the two gen_write_new_pc_* functions and have one as a thin
wrapper around the other.) IDK about the extra overhead from
tcg_gen_addi(), though.
