On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote: > Submitted as an extention to the multi-feature branch maintained > by Jonathan Cameron at: > https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
BTW pls set subject prefix for all patches, and put it before the patch #. -v parameter to format-patch will do this for you. > > Summary of Changes: > 1) E820 CFMW Bug fix. > 2) Add CXL_CAPACITY_MULTIPLIER definition to replace magic numbers > 3) Multi-Region and Volatile Memory support for CXL Type-3 Devices > 4) CXL Type-3 SRAT Generation when NUMA node is attached to memdev > > > Regarding the E820 fix > * This bugfix is required for memory regions to work on x86 > * input from Dan Williams and others suggest that E820 entry for > the CFMW should not exist, as it is expected to be dynamically > assigned at runtime. If this entry exists, it instead blocks > region creation by nature of the memory region being marked as > reserved. > > Regarding Multi-Region and Volatile Memory > * Developed with input from Jonathan Cameron and Davidlohr Bueso. > > Regarding SRAT Generation for Type-3 Devices > * Co-Developed by Davidlohr Bueso. Built from his base patch and > extended to work with both volatile and persistent regions. > * This can be used to demonstrate static type-3 device mapping and > testing numa-access to type-3 device memory regions. > > > This series brings 3 features to CXL Type-3 Devices: > 1) Volatile Memory Region support > 2) Multi-Region support (1 Volatile, 1 Persistent) > 3) (optional) SRAT Entry generation for type-3 device regions > > In this series we implement multi-region and volatile region support > through 7 major changes to CXL devices > 1) The HostMemoryBackend [hostmem] has been replaced by two > [hostvmem] and [hostpmem] to store volatile and persistent > memory respectively > 2) The single AddressSpace has been replaced by two AddressSpaces > [hostvmem_as] and [hostpmem_as] to map respective memdevs. > 3) Each memory region size and total region are stored separately > 4) The CDAT and DVSEC memory map entries have been updated: > a) if vmem is present, vmem is mapped at DPA(0) > b) if pmem is present > i) and vmem is present, pmem is mapped at DPA(vmem->size) > ii) else, pmem is mapped at DPA(0) > c) partitioning of pmem is not supported in this patch set but > has been discussed and this design should suffice. > 5) Read/Write functions have been updated to access AddressSpaces > according to the mapping described in #4 > 6) cxl-mailbox has been updated to report the respective size of > volatile and persistent memory regions > 7) SRAT entries may optionally be generated by manually assigning > memdevs to a cpuless numa node > > To support the Device Physical Address (DPA) Mapping decisions, see > CXL Spec (3.0) Section 8.2.9.8.2.0 - Get Partition Info: > Active Volatile Memory > The device shall provide this volatile capacity starting at DPA 0 > Active Persistent Memory > The device shall provide this persistent capacity starting at the > DPA immediately following the volatile capacity > > Partitioning of Persistent Memory regions may be supported on > following patch sets. > > > Gregory Price (4): > hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios > hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition > hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) > hw/acpi/cxl.c: Fill in SRAT for vmem/pmem if NUMA node is assigned > > docs/system/devices/cxl.rst | 74 ++++++++-- > hw/acpi/cxl.c | 67 +++++++++ > hw/cxl/cxl-mailbox-utils.c | 23 +-- > hw/i386/acpi-build.c | 4 + > hw/i386/pc.c | 2 - > hw/mem/cxl_type3.c | 274 +++++++++++++++++++++++++++--------- > include/hw/acpi/cxl.h | 1 + > include/hw/cxl/cxl_device.h | 11 +- > tests/qtest/cxl-test.c | 111 +++++++++++---- > 9 files changed, 443 insertions(+), 124 deletions(-) > > -- > 2.37.3
