I believe this was dropped from my line because Jonathan carried a similar commit on his branch.
Happy to push it up again as a separate commit if that is what you want. Noted for the future on upstreams -----Original Message----- From: Michael S. Tsirkin <m...@redhat.com> Sent: Wednesday, October 26, 2022 4:06 PM To: Gregory Price <gourry.memve...@gmail.com> Cc: qemu-devel@nongnu.org; jonathan.came...@huawei.com; linux-...@vger.kernel.org; alison.schofi...@intel.com; d...@stgolabs.net; a.manzana...@samsung.com; bwida...@kernel.org; Gregory Price <gregory.pr...@memverge.com> Subject: Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL On Thu, Oct 06, 2022 at 07:37:01PM -0400, Gregory Price wrote: > Current code sets to STORAGE_EXPRESS and then overrides it. > > Signed-off-by: Gregory Price <gregory.pr...@memverge.com> If you expect me to merge it you need to CC me. Also, do we need this separately from the series? > --- > hw/mem/cxl_type3.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index > ada2108fac..1837c1c83a 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > } > > pci_config_set_prog_interface(pci_conf, 0x10); > - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); > > pcie_endpoint_cap_init(pci_dev, 0x80); > cxl_cstate->dvsec_offset = 0x100; @@ -335,7 +334,7 @@ static void > ct3_class_init(ObjectClass *oc, void *data) > > pc->realize = ct3_realize; > pc->exit = ct3_exit; > - pc->class_id = PCI_CLASS_STORAGE_EXPRESS; > + pc->class_id = PCI_CLASS_MEMORY_CXL; > pc->vendor_id = PCI_VENDOR_ID_INTEL; > pc->device_id = 0xd93; /* LVF for now */ > pc->revision = 1; > -- > 2.37.3 > >
