On Tue, Nov 15, 2022 at 10:12 AM Frédéric Pétrot
<frederic.pet...@univ-grenoble-alpes.fr> wrote:
>
> Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
> using numa configuration, e.g.:
> ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
> -m 2G -smp cpus=16 \
> -object memory-backend-ram,id=mem0,size=512M \
> -object memory-backend-ram,id=mem1,size=512M \
> -object memory-backend-ram,id=mem2,size=512M \
> -object memory-backend-ram,id=mem3,size=512M \
> -numa node,cpus=0-3,memdev=mem0,nodeid=0 \
> -numa node,cpus=4-7,memdev=mem1,nodeid=1 \
> -numa node,cpus=8-11,memdev=mem2,nodeid=2 \
> -numa node,cpus=12-15,memdev=mem3,nodeid=3
> leads to:
> Unexpected error in object_property_find_err() at ../qom/object.c:1304:
> qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
> found
>
> This patch makes the nubering of the S irqs identical to what it was before.
>
> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
> Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/intc/sifive_plic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index c2dfacf028..b4949bef97 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -476,11 +476,11 @@ DeviceState *sifive_plic_create(hwaddr addr, char
> *hart_config,
> CPUState *cpu = qemu_get_cpu(cpu_num);
>
> if (plic->addr_config[i].mode == PLICMode_M) {
> - qdev_connect_gpio_out(dev, num_harts - plic->hartid_base +
> cpu_num,
> + qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
> qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
> }
> if (plic->addr_config[i].mode == PLICMode_S) {
> - qdev_connect_gpio_out(dev, cpu_num,
> + qdev_connect_gpio_out(dev, cpu_num - hartid_base,
> qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
> }
> }
> --
> 2.37.2
>
>
