Notice when the host has additional atomic instructions.
The new variables will also be used in generated code.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
tcg/aarch64/tcg-target.h | 3 +++
tcg/aarch64/tcg-target.c.inc | 10 ++++++++++
2 files changed, 13 insertions(+)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 0dff5807f6..b8f734f371 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -57,6 +57,9 @@ typedef enum {
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
+extern bool have_lse;
+extern bool have_lse2;
+
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 001a71bbc0..cf5ee6f742 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -13,6 +13,8 @@
#include "../tcg-ldst.c.inc"
#include "../tcg-pool.c.inc"
#include "qemu/bitops.h"
+#include <asm/hwcap.h>
+
/* We're going to re-use TCGType in setting of the SF bit, which controls
the size of the operation performed. If we know the values match, it
@@ -71,6 +73,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind
kind, int slot)
return TCG_REG_X0 + slot;
}
+bool have_lse;
+bool have_lse2;
+
#define TCG_REG_TMP TCG_REG_X30
#define TCG_VEC_TMP TCG_REG_V31
@@ -2918,6 +2923,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
static void tcg_target_init(TCGContext *s)
{
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+
+ have_lse = hwcap & HWCAP_ATOMICS;
+ have_lse2 = hwcap & HWCAP_USCAT;
+
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
--
2.34.1
