On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale <mchit...@ventanamicro.com> wrote: > > If smstateen is implemented and sstateen0.fcsr is clear then the floating > point > operations must return illegal instruction exception or virtual instruction > trap, if relevant. > > Signed-off-by: Mayuresh Chitale <mchit...@ventanamicro.com> > Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn> > --- > target/riscv/csr.c | 23 ++++++++++++ > target/riscv/insn_trans/trans_rvf.c.inc | 43 +++++++++++++++++++++-- > target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++ > 3 files changed, 75 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 71236f2b5d..8b25f885ec 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) > !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { > return RISCV_EXCP_ILLEGAL_INST; > } > + > + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); > + } > #endif > return RISCV_EXCP_NONE; > } > @@ -2023,6 +2027,9 @@ static RISCVException write_mstateen0(CPURISCVState > *env, int csrno, > target_ulong new_val) > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > > return write_mstateen(env, csrno, wr_mask, new_val); > } > @@ -2059,6 +2066,10 @@ static RISCVException write_mstateen0h(CPURISCVState > *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_mstateenh(env, csrno, wr_mask, new_val); > } > > @@ -2096,6 +2107,10 @@ static RISCVException write_hstateen0(CPURISCVState > *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_hstateen(env, csrno, wr_mask, new_val); > } > > @@ -2135,6 +2150,10 @@ static RISCVException write_hstateen0h(CPURISCVState > *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_hstateenh(env, csrno, wr_mask, new_val); > } > > @@ -2182,6 +2201,10 @@ static RISCVException write_sstateen0(CPURISCVState > *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_sstateen(env, csrno, wr_mask, new_val); > } > > diff --git a/target/riscv/insn_trans/trans_rvf.c.inc > b/target/riscv/insn_trans/trans_rvf.c.inc > index a1d3eb52ad..93657680c6 100644 > --- a/target/riscv/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > @@ -24,9 +24,46 @@ > return false; \ > } while (0) > > -#define REQUIRE_ZFINX_OR_F(ctx) do {\ > - if (!ctx->cfg_ptr->ext_zfinx) { \ > - REQUIRE_EXT(ctx, RVF); \ > +#ifndef CONFIG_USER_ONLY > +static inline bool smstateen_fcsr_check(DisasContext *ctx, int index) > +{ > + CPUState *cpu = ctx->cs; > + CPURISCVState *env = cpu->env_ptr; > + uint64_t stateen = env->mstateen[index];
Sorry I missed this the first time around. You can't access env here Richard pointed it out here: https://patchwork.kernel.org/project/qemu-devel/patch/20221117070316.58447-8-liwei...@iscas.ac.cn/#25095773 I'm going to drop this patch and patch v5 Alistair