The new select instruction provides two separate register inputs, whereas the old load-on-condition instruction overlaps one of the register inputs with the destination.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- tcg/s390x/tcg-target.c.inc | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b2adbbe7de..1e4947b598 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -204,6 +204,8 @@ typedef enum S390Opcode { RRFa_XRK = 0xb9f7, RRFa_XGRK = 0xb9e7, + RRFam_SELGR = 0xb9e3, + RRFc_LOCR = 0xb9f2, RRFc_LOCGR = 0xb9e2, @@ -560,12 +562,20 @@ static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, tcg_out32(s, (op << 16) | (r1 << 4) | r2); } +/* RRF-a without the m4 field */ static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2, TCGReg r3) { tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); } +/* RRF-a with the m4 field */ +static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, + TCGReg r1, TCGReg r2, TCGReg r3, int m4) +{ + tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); +} + static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2, int m3) { @@ -1474,6 +1484,17 @@ static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, return; } + /* Note that while MIE3 implies LOC, it does not imply LOC2. */ + if (HAVE_FACILITY(MISC_INSN_EXT3)) { + if (v3const) { + tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); + v3 = TCG_TMP0; + } + /* Emit: dest = cc ? v3 : v4. */ + tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); + return; + } + if (HAVE_FACILITY(LOAD_ON_COND)) { if (dest == v4) { if (v3const) { -- 2.34.1