> -----Original Message-----
> From: Mukilan Thiyagarajan (QUIC) <quic_mthiy...@quicinc.com>
> Sent: Tuesday, December 27, 2022 9:35 AM
> To: qemu-devel@nongnu.org; Taylor Simpson <tsimp...@quicinc.com>;
> laur...@vivier.eu
> Cc: Brian Cain <bc...@quicinc.com>; richard.hender...@linaro.org;
> alex.ben...@linaro.org; Mukilan Thiyagarajan (QUIC)
> <quic_mthiy...@quicinc.com>
> Subject: [PATCH 2/2] target/hexagon: rename aliased register
> HEX_REG_P3_0
>
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index
> 658ca4ff78..807037c586 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -86,7 +86,7 @@ static target_ulong adjust_stack_ptrs(CPUHexagonState
> *env, target_ulong addr)
> return addr;
> }
>
> -/* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */
> +/* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate
> +registers */
Not sure why you broke this comment into two lines, but ...
/*
* Multiline comments should be
* formatted like this
*/
Otherwise
Reviewed-by: Taylor Simpson <tsimp...@quicinc.com>
