Hi Daniel, On Thu, Dec 29, 2022 at 4:21 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > > > On 12/28/22 12:18, Bin Meng wrote: > > On Wed, Dec 28, 2022 at 9:38 PM Daniel Henrique Barboza > > <dbarb...@ventanamicro.com> wrote: > >> This test is used to do a quick sanity check to ensure that we're able > >> to run the existing QEMU FW image. > >> > >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > >> RISCV32_BIOS_BIN firmware with minimal options. > >> > >> The riscv32 'spike' machine isn't bootable at this moment, requiring an > >> Opensbi fix [1] and QEMU side changes [2]. We could just leave at that > > nits: OpenSBI > > > >> or add a 'skip' test to remind us about it. To work as a reminder that > >> we have a riscv32 'spike' test that should be enabled as soon as Opensbi > > ditto > > > >> QEMU rom receives the fix, we're adding a 'skip' test: > >> > >> (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike: > >> SKIP: requires OpenSBI fix to work > >> > >> [1] > >> https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bm...@tinylab.org/ > >> [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 > >> > >> Cc: Cleber Rosa <cr...@redhat.com> > >> Cc: Philippe Mathieu-Daudé <phi...@linaro.org> > >> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > >> --- > >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > >> 1 file changed, 65 insertions(+) > >> create mode 100644 tests/avocado/riscv_opensbi.py > >> > >> diff --git a/tests/avocado/riscv_opensbi.py > >> b/tests/avocado/riscv_opensbi.py > >> new file mode 100644 > >> index 0000000000..3549d36a11 > >> --- /dev/null > >> +++ b/tests/avocado/riscv_opensbi.py > >> @@ -0,0 +1,65 @@ > >> +# OpenSBI boot test for RISC-V machines > >> +# > >> +# Copyright (c) 2022, Ventana Micro > >> +# > >> +# This work is licensed under the terms of the GNU GPL, version 2 or > >> +# later. See the COPYING file in the top-level directory. > >> + > >> +from avocado_qemu import QemuSystemTest > >> +from avocado import skip > >> +from avocado_qemu import wait_for_console_pattern > >> + > >> +class RiscvOpensbi(QemuSystemTest): > >> + """ > >> + :avocado: tags=accel:tcg > >> + """ > >> + timeout = 5 > >> + > >> + def boot_opensbi(self): > >> + self.vm.set_console() > >> + self.vm.launch() > >> + wait_for_console_pattern(self, 'Platform Name') > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > >> + > >> + def test_riscv64_virt(self): > >> + """ > >> + :avocado: tags=arch:riscv64 > >> + :avocado: tags=machine:virt > >> + """ > >> + self.boot_opensbi() > >> + > >> + def test_riscv64_spike(self): > >> + """ > >> + :avocado: tags=arch:riscv64 > >> + :avocado: tags=machine:spike > >> + """ > >> + self.boot_opensbi() > >> + > >> + def test_riscv64_sifive_u(self): > >> + """ > >> + :avocado: tags=arch:riscv64 > >> + :avocado: tags=machine:sifive_u > >> + """ > >> + self.boot_opensbi() > > nits: could we keep both 64-bit and 32-bit machines in the same order? > > e.g.: virt, sifive_u, spike > > I've changed the order to be first the default machine (spike), then the other > machines in alphabetic order. > > I've also put the 32 and 64 bit tests for the same machine one after the > other: > > (06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike: > SKIP: requires OpenSBI fix to work > (07/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv64_spike: > PASS (0.04 s) > (08/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_sifive_u: > PASS (0.07 s) > (09/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv64_sifive_u: > PASS (0.07 s) > (10/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_virt: PASS > (0.05 s) > (11/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv64_virt: PASS > (0.05 s) > > > > If that's ok I'll send v4 tomorrow. >
Thanks, that looks good to me. Regards, Bin