On Mon, 28 Nov 2022 10:01:56 -0500 Gregory Price <gourry.memve...@gmail.com> wrote:
> Defines are starting to exceed line length limits, align them for > cleanliness before making modifications. > > Signed-off-by: Gregory Price <gregory.pr...@memverge.com> Hi Gregory, I was just reordering my tree and noticed that you've only gone with 2 space indent. Given 4 spaces is the convention in QEMU for other uses, I've switched my local copy of this over to 4 spaces. Note there was also a single inconsistent 1 space indent - see below. Jonathan > > --- > tests/qtest/cxl-test.c | 99 +++++++++++++++++++++++------------------- > 1 file changed, 54 insertions(+), 45 deletions(-) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index c54f18e76b..e59ba22387 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -8,55 +8,64 @@ > #include "qemu/osdep.h" > #include "libqtest-single.h" > > -#define QEMU_PXB_CMD "-machine q35,cxl=on " \ > - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > - "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G " > - > -#define QEMU_2PXB_CMD "-machine q35,cxl=on " \ > - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > - "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > - "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > - > -#define QEMU_VIRT_2PXB_CMD "-machine virt,cxl=on " \ > - "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > - "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > - "-M > cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > - > -#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > +#define QEMU_PXB_CMD \ > + "-machine q35,cxl=on " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G " > + > +#define QEMU_2PXB_CMD \ > + "-machine q35,cxl=on " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "- M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " This one only has one space. > + > +#define QEMU_VIRT_2PXB_CMD \ > + "-machine virt,cxl=on " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > + > +#define QEMU_RP \ > + "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > > /* Dual ports on first pxb */ > -#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ > - "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " > +#define QEMU_2RP \ > + "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ > + "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " > > /* Dual ports on each of the pxb instances */ > -#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ > - "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \ > - "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \ > - "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 " > - > -#define QEMU_T3D "-object > memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ > - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M > " \ > - "-device > cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " > - > -#define QEMU_2T3D "-object > memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ > - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M > " \ > - "-device > cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \ > - "-object > memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \ > - "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M > " \ > - "-device > cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " > - > -#define QEMU_4T3D "-object > memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ > - "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M > " \ > - "-device > cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \ > - "-object > memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \ > - "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M > " \ > - "-device > cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \ > - "-object > memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \ > - "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M > " \ > - "-device > cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \ > - "-object > memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \ > - "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M > " \ > - "-device > cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 " > +#define QEMU_4RP \ > + "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \ > + "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \ > + "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \ > + "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 " > + > +#define QEMU_T3D \ > + "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ > + "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ > + "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " > + > +#define QEMU_2T3D \ > + "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ > + "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ > + "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \ > + "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \ > + "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \ > + "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " > + > +#define QEMU_4T3D \ > + "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \ > + "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \ > + "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \ > + "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \ > + "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \ > + "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \ > + "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \ > + "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M " \ > + "-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \ > + "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \ > + "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \ > + "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 " > > static void cxl_basic_hb(void) > {