From: Anup Patel <apa...@ventanamicro.com> We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel <apa...@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-Id: <20221108125703.1463577-2-apa...@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 71236f2b5d..0db2c233e5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -940,7 +940,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno) } if (riscv_cpu_virt_enabled(env)) { - if (!(get_field(env->hcounteren, COUNTEREN_TM) & + if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } -- 2.39.0