On Sat, Dec 24, 2022 at 4:08 AM Christoph Muellner
<christoph.muell...@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muell...@vrull.eu>
>
> This patch adds support for the XTheadCondMov ISA extension.
> The patch uses the T-Head specific decoder and translation.
>
> Changes in v2:
> - Add ISA_EXT_DATA_ENTRY()
> - Fix invalid use of register from dest_gpr()
> - Use single decoder for XThead extensions
>
> Co-developed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
> Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++
> target/riscv/translate.c | 2 +-
> target/riscv/xthead.decode | 4 +++
> 5 files changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 17273425a8..36a53784dd 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -112,6 +112,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
> ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
> ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
> + ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0,
> ext_xtheadcondmov),
> ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0,
> ext_xtheadsync),
> ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0,
> ext_XVentanaCondOps),
> };
> @@ -1069,6 +1070,7 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
> DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
> DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
> + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov,
> false),
> DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
> DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
> false),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5f68cb1e1e..01f035d8e9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -469,6 +469,7 @@ struct RISCVCPUConfig {
> bool ext_xtheadbb;
> bool ext_xtheadbs;
> bool ext_xtheadcmo;
> + bool ext_xtheadcondmov;
> bool ext_xtheadsync;
> bool ext_XVentanaCondOps;
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
> b/target/riscv/insn_trans/trans_xthead.c.inc
> index fb1f2c5731..bf549bbd74 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -40,6 +40,12 @@
> } \
> } while (0)
>
> +#define REQUIRE_XTHEADCONDMOV(ctx) do { \
> + if (!ctx->cfg_ptr->ext_xtheadcondmov) { \
> + return false; \
> + } \
> +} while (0)
> +
> #define REQUIRE_XTHEADSYNC(ctx) do { \
> if (!ctx->cfg_ptr->ext_xtheadsync) { \
> return false; \
> @@ -272,6 +278,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO,
> REQUIRE_PRIV_MHS)
> NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
>
> +/* XTheadCondMov */
> +
> +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond)
> +{
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> + TCGv old = get_gpr(ctx, a->rd, EXT_NONE);
> + TCGv dest = dest_gpr(ctx, a->rd);
> +
> + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old);
> +
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +/* th.mveqz: "if (rs2 == 0) rd = rs1;" */
> +static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a)
> +{
> + REQUIRE_XTHEADCONDMOV(ctx);
> + return gen_th_condmove(ctx, a, TCG_COND_EQ);
> +}
> +
> +/* th.mvnez: "if (rs2 != 0) rd = rs1;" */
> +static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
> +{
> + REQUIRE_XTHEADCONDMOV(ctx);
> + return gen_th_condmove(ctx, a, TCG_COND_NE);
> +}
> +
> /* XTheadSync */
>
> static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index fc326e0a79..f15883b16b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -129,7 +129,7 @@ static bool has_xthead_p(DisasContext *ctx
> __attribute__((__unused__)))
> {
> return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
> ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
> - ctx->cfg_ptr->ext_xtheadsync;
> + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync;
> }
>
> #define MATERIALISE_EXT_PREDICATE(ext) \
> diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
> index 8494805611..a8ebd8a18b 100644
> --- a/target/riscv/xthead.decode
> +++ b/target/riscv/xthead.decode
> @@ -84,6 +84,10 @@ th_l2cache_call 0000000 10101 00000 000 00000 0001011
> th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
> th_l2cache_iall 0000000 10110 00000 000 00000 0001011
>
> +# XTheadCondMov
> +th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r
> +th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r
> +
> # XTheadSync
> th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
> th_sync 0000000 11000 00000 000 00000 0001011
> --
> 2.38.1
>
>
