From: Christoph Müllner <christoph.muell...@vrull.eu>
This patch adds support for the T-Head FMemIdx instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use single decoder for XThead extensions
- Use get_th_address_indexed for address calculations
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++
target/riscv/translate.c | 3 +-
target/riscv/xthead.decode | 10 ++
5 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2d5a0881f1..5679e2cb83 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0,
ext_xtheadcondmov),
+ ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0,
ext_xtheadfmemidx),
ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0,
ext_xtheadmemidx),
ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0,
ext_xtheadmempair),
@@ -1102,6 +1103,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
+ DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d776fea760..5cc3011529 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -478,6 +478,7 @@ struct RISCVCPUConfig {
bool ext_xtheadbs;
bool ext_xtheadcmo;
bool ext_xtheadcondmov;
+ bool ext_xtheadfmemidx;
bool ext_xtheadmac;
bool ext_xtheadmemidx;
bool ext_xtheadmempair;
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn_trans/trans_xthead.c.inc
index 8167de0393..37373732f6 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -46,6 +46,12 @@
} \
} while (0)
+#define REQUIRE_XTHEADFMEMIDX(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_XTHEADMAC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadmac) { \
return false; \
@@ -341,6 +347,108 @@ static bool trans_th_mvnez(DisasContext *ctx,
arg_th_mveqz *a)
return gen_th_condmove(ctx, a, TCG_COND_NE);
}
+/* XTheadFMem */
+
+/*
+ * Load 64-bit float from indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+ bool zext_offs)
+{
+ TCGv_i64 rd = cpu_fpr[a->rd];
+ TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2,
zext_offs);
+
+ tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);
+ if ((memop & MO_SIZE) == MO_32) {
+ gen_nanbox_s(rd, rd);
+ }
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+/*
+ * Store 64-bit float to indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+ bool zext_offs)
+{
+ TCGv_i64 rd = cpu_fpr[a->rd];
+ TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2,
zext_offs);
+
+ tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);
+
+ return true;
+}
+
+static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fload_idx(ctx, a, MO_TEUQ, false);
+}
+
+static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fload_idx(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fload_idx(ctx, a, MO_TEUQ, true);
+}
+
+static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fload_idx(ctx, a, MO_TEUL, true);
+}
+
+static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fstore_idx(ctx, a, MO_TEUQ, false);
+}
+
+static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fstore_idx(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ return gen_fstore_idx(ctx, a, MO_TEUQ, true);
+}
+
+static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
+{
+ REQUIRE_XTHEADFMEMIDX(ctx);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ return gen_fstore_idx(ctx, a, MO_TEUL, true);
+}
+
/* XTheadMac */
static bool gen_th_mac(DisasContext *ctx, arg_r *a,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a979d43a6a..216eaf9d12 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx
__attribute__((__unused__)))
{
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
- ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
+ ctx->cfg_ptr->ext_xtheadcondmov ||
+ ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac ||
ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair ||
ctx->cfg_ptr->ext_xtheadsync;
}
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index 69e40f22dc..81daf1d694 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -100,6 +100,16 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011
th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r
th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r
+# XTheadFMemIdx
+th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx
+th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx
+th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx
+th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx
+th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx
+
# XTheadMac
th_mula 00100 00 ..... ..... 001 ..... 0001011 @r
th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r
--
2.39.1
