On Thu, Feb 02, 2023 at 10:58:07AM -0300, Daniel Henrique Barboza wrote: > Hi, > > This new version removed the translate_fn() from patch 1 because it > wasn't removing the sign-extension for pentry as we thought it would. > A more detailed explanation is given in the commit msg of patch 1. > > We're now retrieving the 'lowaddr' value from load_elf_ram_sym() and > using it when we're running a 32-bit CPU. This worked with 32 bit > 'virt' machine booting with the -kernel option. > > If this approach doesn't work for the Xvisor use case, IMO we should > just filter kernel_load_addr bits directly as we were doing a handful of > versions ago. > > Patches are based on current riscv-to-apply.next. > > Changes from v9: > - patch 1: > - removed the translate_fn() callback > - return 'kernel_low' when running a 32-bit CPU > - v9 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04509.html
I think my T-b got lost last time around, but I gave this version a whirl too & things are working for me as they were before on Icicle. For the series: Tested-by: Conor Dooley <conor.doo...@microchip.com> Thanks, Conor. > > Daniel Henrique Barboza (3): > hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel() > hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() > hw/riscv/boot.c: make riscv_load_initrd() static > > hw/riscv/boot.c | 96 +++++++++++++++++++++++--------------- > hw/riscv/microchip_pfsoc.c | 12 +---- > hw/riscv/opentitan.c | 4 +- > hw/riscv/sifive_e.c | 4 +- > hw/riscv/sifive_u.c | 12 +---- > hw/riscv/spike.c | 14 ++---- > hw/riscv/virt.c | 12 +---- > include/hw/riscv/boot.h | 3 +- > 8 files changed, 76 insertions(+), 81 deletions(-) > > -- > 2.39.1 > >
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