On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp
flag. Use the flag directly.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Regards,
Weiwei Li
---
target/riscv/cpu.c | 10 +++-------
target/riscv/cpu.h | 1 -
target/riscv/csr.c | 2 +-
target/riscv/pmp.c | 4 ++--
4 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e67e72f90..430b6adccb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_set_feature(env, RISCV_FEATURE_PMP);
}
- if (cpu->cfg.epmp) {
- riscv_set_feature(env, RISCV_FEATURE_EPMP);
-
+ if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
- if (!cpu->cfg.pmp) {
- error_setg(errp, "Invalid configuration: EPMP requires PMP
support");
- return;
- }
+ error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+ return;
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 46de6f2f7f..d0de11fd41 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -88,7 +88,6 @@
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
- RISCV_FEATURE_EPMP,
};
/* Privileged specification version */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index af4a44b33b..5b974dad6b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
static RISCVException epmp(CPURISCVState *env, int csrno)
{
- if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
+ if (env->priv == PRV_M && riscv_cpu_cfg(env).epmp) {
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 4bc4113531..bb54899635 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t
pmp_index, uint8_t val)
if (pmp_index < MAX_RISCV_PMPS) {
bool locked = true;
- if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+ if (riscv_cpu_cfg(env).epmp) {
/* mseccfg.RLB is set */
if (MSECCFG_RLB_ISSET(env)) {
locked = false;
@@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env,
target_ulong addr,
{
bool ret;
- if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+ if (riscv_cpu_cfg(env).epmp) {
if (MSECCFG_MMWP_ISSET(env)) {
/*
* The Machine Mode Whitelist Policy (mseccfg.MMWP) is set