Raise SIGFPE for ieee exceptions.
The other types, such as FSR_FTT_UNIMPFPOP, should not appear,
because we enable normal emulation of missing insns at the
start of sparc_cpu_realizefn().
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/cpu.h | 3 +--
linux-user/sparc/cpu_loop.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index e478c5eb16..ae8de606d5 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -197,8 +197,7 @@ enum {
#define FSR_FTT2 (1ULL << 16)
#define FSR_FTT1 (1ULL << 15)
#define FSR_FTT0 (1ULL << 14)
-//gcc warns about constant overflow for ~FSR_FTT_MASK
-//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#ifdef TARGET_SPARC64
#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
index 093358a39a..5a8a71e976 100644
--- a/linux-user/sparc/cpu_loop.c
+++ b/linux-user/sparc/cpu_loop.c
@@ -297,6 +297,28 @@ void cpu_loop (CPUSPARCState *env)
restore_window(env);
break;
+ case TT_FP_EXCP:
+ {
+ int code = TARGET_FPE_FLTUNK;
+ target_ulong fsr = env->fsr;
+
+ if ((fsr & FSR_FTT_MASK) == FSR_FTT_IEEE_EXCP) {
+ if (fsr & FSR_NVC) {
+ code = TARGET_FPE_FLTINV;
+ } else if (fsr & FSR_OFC) {
+ code = TARGET_FPE_FLTOVF;
+ } else if (fsr & FSR_UFC) {
+ code = TARGET_FPE_FLTUND;
+ } else if (fsr & FSR_DZC) {
+ code = TARGET_FPE_FLTDIV;
+ } else if (fsr & FSR_NXC) {
+ code = TARGET_FPE_FLTRES;
+ }
+ }
+ force_sig_fault(TARGET_SIGFPE, code, env->pc);
+ }
+ break;
+
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
--
2.34.1
