On 2/24/23 21:29, Igor Mammedov wrote:
On Tue, 21 Feb 2023 23:04:57 +0700
Bui Quang Minh <minhquangbu...@gmail.com> wrote:
This commit refactors APIC registers read/write function to support both
MMIO read/write in xAPIC mode and MSR read/write in x2APIC mode. Also,
support larger APIC ID, self IPI, new IPI destination determination in
x2APIC mode.
Signed-off-by: Bui Quang Minh <minhquangbu...@gmail.com>
---
hw/intc/apic.c | 211 +++++++++++++++++++++++++-------
hw/intc/apic_common.c | 2 +-
include/hw/i386/apic.h | 5 +-
include/hw/i386/apic_internal.h | 2 +-
4 files changed, 172 insertions(+), 48 deletions(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 2d3e55f4e2..205d5923ec 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -30,6 +30,7 @@
#include "hw/i386/apic-msidef.h"
#include "qapi/error.h"
#include "qom/object.h"
+#include "tcg/helper-tcg.h"
#define MAX_APICS 255
I'm curious how does it work without increasing ^^^?
Hmm, my commit message is not entirely correct. In this series, some
operations (send IPI, IPI destination determination) have been updated
to support x2APIC mode. However, the emulated APIC still doesn't support
APIC ID larger than 255 because currently, we use a fixed length (255 +
1) array to manage local APICs. So to support larger APIC ID, I think we
need to find any way to manage those, as the possible allocated APIC ID
range is large and maybe the allocated APIC ID is sparse which makes
fixed length array so wasteful.
Thanks,
Quang Minh.
