On Wed, 2023-03-01 at 14:18 +0100, BALATON Zoltan wrote: > > Are you sure the PIC ELCR is actually set for the lines you're having > > trouble with? Is that something the Pegasos SmartFirmware would have > > done, and MorphOS is expecting to inherit but isn't actually setting up > > for itself? > > No, it works with other guests like Linux and AmigaOS that use PIC as set > up by the firmware but MorphOS tries to use it in level sensitive mode and > likely has an IRQ handler which expects this to work. This is where I've > debugged it and came to this workaround: > > https://lists.nongnu.org/archive/html/qemu-ppc/2023-02/msg00403.html > > When booting MorphOS with -d unimp I see these logs: > > i8259: level sensitive irq not supported > i8259: level sensitive irq not supported > > which is I guess when it tries to set it for both PICs. (If you want to > try this MorphOS iso is downloadable and instructions how to boot it is > here: http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
Wow. Even looking at the PIIX3 datasheet from 1996, That 'Edge/Level Bank Select (LTIM)' bit was documented as 'This bit is disabled. Its function is replaced by the Edge/Level Triggerede Control (ELCR) Registers. We've been able to set the edge/level on a per-pin basis ever since the ELCR was introduced with the IBM PS/2, I think. It isn't a *correct* fix without a little bit more typing, but does this make it work? diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 17910f3bcb..36ebcff025 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -246,6 +246,7 @@ static void pic_ioport_write(void *opaque, hwaddr addr64, if (val & 0x08) { qemu_log_mask(LOG_UNIMP, "i8259: level sensitive irq not supported\n"); + s->elcr = 0xff; } } else if (val & 0x08) { if (val & 0x04) {
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