On Tue, 14 Feb 2023 18:05:25 PST (-0800), liwei...@iscas.ac.cn wrote:
Specification for Zv* extensions can be found in:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zvfh-upstream-v2
v2:
* improve the error message for vector related check suggested by Daniel
Henrique Barboza in patch 5
* add similar simplification for check in csr.c/cpu_helper.c in patch 8
* fix typos in commit messages
Weiwei Li (14):
target/riscv: Fix the relationship between Zfhmin and Zfh
target/riscv: Fix the relationship between Zhinxmin and Zhinx
target/riscv: Simplify the check for Zfhmin and Zhinxmin
target/riscv: Add cfg properties for Zv* extensions
target/riscv: Fix relationship between V, Zve*, F and D
target/riscv: Add propertie check for Zvfh{min} extensions
target/riscv: Indent fixes in cpu.c
target/riscv: Simplify check for Zve32f and Zve64f
target/riscv: Replace check for F/D to Zve32f/Zve64d in
trans_rvv.c.inc
target/riscv: Remove rebundunt check for zve32f and zve64f
target/riscv: Add support for Zvfh/zvfhmin extensions
target/riscv: Fix check for vector load/store instructions when EEW=64
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
target/riscv: Expose properties for Zv* extensions
target/riscv/cpu.c | 99 ++++++++----
target/riscv/cpu.h | 3 +
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 3 +-
target/riscv/insn_trans/trans_rvv.c.inc | 184 +++++++---------------
target/riscv/insn_trans/trans_rvzfh.c.inc | 25 ++-
6 files changed, 146 insertions(+), 170 deletions(-)
Thanks, I queued this up. There were a few more spelling errors in the
commit messages, I just cleaned those up while merging.
