On Fri, 24 Feb 2023 05:25:32 PST (-0800), dbarb...@ventanamicro.com wrote:
Hi,This version has a change in patch 2, proposed by Weiwei Li, where we're now triggering virt_instruction_fault before triggering illegal_insn fault from S mode. Richard already queued patch 1 is queued in tcg-next already. I'm still including it here to allow for easier testing of the remaining patches. Changes from v7: - patch 1: queued in tcg-next, included here to facilitate testing the other patches - patch 2: - changed check_zicbo_envcfg() to trigger the virtual faults before triggering the illegal exception from S mode. - v7 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg07041.html Christoph Muellner (3): target/riscv: implement Zicboz extension target/riscv: implement Zicbom extension target/riscv: add Zicbop cbo.prefetch{i,r,m} placeholder Daniel Henrique Barboza (1): tcg: add 'size' param to probe_access_flags() accel/stubs/tcg-stub.c | 2 +- accel/tcg/cputlb.c | 17 ++- accel/tcg/user-exec.c | 5 +- include/exec/exec-all.h | 3 +- semihosting/uaccess.c | 2 +- target/arm/ptw.c | 2 +- target/arm/sve_helper.c | 2 +- target/riscv/cpu.c | 7 + target/riscv/cpu.h | 4 + target/riscv/helper.h | 5 + target/riscv/insn32.decode | 16 ++- target/riscv/insn_trans/trans_rvzicbo.c.inc | 57 +++++++++ target/riscv/op_helper.c | 135 ++++++++++++++++++++ target/riscv/translate.c | 1 + target/s390x/tcg/mem_helper.c | 6 +- 15 files changed, 250 insertions(+), 14 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
Thanks, 2-4 are queued up in riscv-to-apply.next (1 made it already via the TCG tree).
