On 01/27/2012 08:03 AM, Andreas Färber wrote:
Am 27.01.2012 14:07, schrieb Anthony Liguori:
[...] My guess is that a SuperIO
chip could be an ISADevice and that we could simply make the PIIX3 has-a
SuperIO. Then the ISAPC would have a trivial ISA chipset that has-a
SuperIO.
That sounds pretty much like our construction site for PReP...
Yup. It basically boils down to:
Root Complex[1] (PCI Host)
- Northbridge (Memory Controller)
- Southbridge (Super I/O chip)
Most platforms will follow this type of composition model with peripheral
devices hanging off a bus in the Southbridge or directly from the Root Complex.
Would you say that the SuperIO is-a ISADevice
The SuperIO device is-a Root Complex device. With the I440FX, the Root Complex
was PCI bus so the SuperIO chip (the PIIX3) is-a PCIDevice. In older PCIs, the
Root Complex was ISA (sort of).
[1] A better name for this is System Bus but I'm using Root Complex to avoid
confusion with sysbus.
But for the PC, we can make the SuperIO chip be is-a DeviceState and just have
it expose a MemoryRegion and a bunch of IRQs. That would trivialize the
implementation of an PIIX3 such that it has-a PCSuperIO and then just routes
IRQs appropriately.
and has-a ISADevice or
would you want to remodel all ISADevices associated with a Super I/O
chipset as private devices to mess with their internals without the
whole enable/disable, etc. ugliness we ran into?
I somewhat doubt that we can find a generic "SuperIO" base class btw.
Right, it's unlikely that a PC SuperIO chip would be useful outside of a PC.
But you may find certain classes of platforms all have a common SuperI/O chip
and can model similar things.
Regards,
Anthony Liguori
Andreas