This patch includes: - VSIGNCOV.{B/H/W/D}. Signed-off-by: Song Gao <gaos...@loongson.cn> --- target/loongarch/disas.c | 5 ++ target/loongarch/helper.h | 5 ++ target/loongarch/insn_trans/trans_lsx.c.inc | 54 +++++++++++++++++++++ target/loongarch/insns.decode | 5 ++ target/loongarch/lsx_helper.c | 19 ++++++++ 5 files changed, 88 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 412c1cedcb..46e808c321 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1079,3 +1079,8 @@ INSN_LSX(vexth_hu_bu, vv) INSN_LSX(vexth_wu_hu, vv) INSN_LSX(vexth_du_wu, vv) INSN_LSX(vexth_qu_du, vv) + +INSN_LSX(vsigncov_b, vvv) +INSN_LSX(vsigncov_h, vvv) +INSN_LSX(vsigncov_w, vvv) +INSN_LSX(vsigncov_d, vvv) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 0876aa3331..a7394b2eb7 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -353,3 +353,8 @@ DEF_HELPER_3(vexth_hu_bu, void, env, i32, i32) DEF_HELPER_3(vexth_wu_hu, void, env, i32, i32) DEF_HELPER_3(vexth_du_wu, void, env, i32, i32) DEF_HELPER_3(vexth_qu_du, void, env, i32, i32) + +DEF_HELPER_FLAGS_4(vsigncov_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(vsigncov_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(vsigncov_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(vsigncov_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index f6058c1360..865485ea10 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -2507,3 +2507,57 @@ TRANS(vexth_hu_bu, gen_vv, gen_helper_vexth_hu_bu) TRANS(vexth_wu_hu, gen_vv, gen_helper_vexth_wu_hu) TRANS(vexth_du_wu, gen_vv, gen_helper_vexth_du_wu) TRANS(vexth_qu_du, gen_vv, gen_helper_vexth_qu_du) + +static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t1, t2; + + t1 = tcg_temp_new_vec_matching(t); + t2 = tcg_temp_new_vec_matching(t); + + tcg_gen_neg_vec(vece, t1, b); + tcg_gen_dupi_vec(vece, t2, 0); + tcg_gen_cmpsel_vec(TCG_COND_LT, vece, t, a, t2, t1, b); + tcg_gen_cmpsel_vec(TCG_COND_EQ, vece, t, a, t2, t2, t); +} + +static void do_vsigncov(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, + uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { + INDEX_op_neg_vec, INDEX_op_cmpsel_vec, 0 + }; + static const GVecGen3 op[4] = { + { + .fniv = gen_vsigncov, + .fno = gen_helper_vsigncov_b, + .opt_opc = vecop_list, + .vece = MO_8 + }, + { + .fniv = gen_vsigncov, + .fno = gen_helper_vsigncov_h, + .opt_opc = vecop_list, + .vece = MO_16 + }, + { + .fniv = gen_vsigncov, + .fno = gen_helper_vsigncov_w, + .opt_opc = vecop_list, + .vece = MO_32 + }, + { + .fniv = gen_vsigncov, + .fno = gen_helper_vsigncov_d, + .opt_opc = vecop_list, + .vece = MO_64 + }, + }; + + tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); +} + +TRANS(vsigncov_b, gvec_vvv, MO_8, do_vsigncov) +TRANS(vsigncov_h, gvec_vvv, MO_16, do_vsigncov) +TRANS(vsigncov_w, gvec_vvv, MO_32, do_vsigncov) +TRANS(vsigncov_d, gvec_vvv, MO_64, do_vsigncov) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 39c582d098..4233dd7404 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -778,3 +778,8 @@ vexth_hu_bu 0111 00101001 11101 11100 ..... ..... @vv vexth_wu_hu 0111 00101001 11101 11101 ..... ..... @vv vexth_du_wu 0111 00101001 11101 11110 ..... ..... @vv vexth_qu_du 0111 00101001 11101 11111 ..... ..... @vv + +vsigncov_b 0111 00010010 11100 ..... ..... ..... @vvv +vsigncov_h 0111 00010010 11101 ..... ..... ..... @vvv +vsigncov_w 0111 00010010 11110 ..... ..... ..... @vvv +vsigncov_d 0111 00010010 11111 ..... ..... ..... @vvv diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c index 9a0b358576..b3a9b8cb66 100644 --- a/target/loongarch/lsx_helper.c +++ b/target/loongarch/lsx_helper.c @@ -871,3 +871,22 @@ VEXTH(vexth_d_w, 64, int64_t, int32_t, D, W) VEXTH(vexth_hu_bu, 16, uint16_t, uint8_t, H, B) VEXTH(vexth_wu_hu, 32, uint32_t, uint16_t, W, H) VEXTH(vexth_du_wu, 64, uint64_t, uint32_t, D, W) + +#define DO_SIGNCOV(a, b) (a == 0 ? 0 : a < 0 ? -b : b) + +#define VSIGNCOV(NAME, BIT, E, DO_OP) \ +void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \ +{ \ + int i; \ + VReg *Vd = (VReg *)vd; \ + VReg *Vj = (VReg *)vj; \ + VReg *Vk = (VReg *)vk; \ + for (i = 0; i < LSX_LEN/BIT; i++) { \ + Vd->E(i) = DO_OP(Vj->E(i), Vk->E(i)); \ + } \ +} + +VSIGNCOV(vsigncov_b, 8, B, DO_SIGNCOV) +VSIGNCOV(vsigncov_h, 16, H, DO_SIGNCOV) +VSIGNCOV(vsigncov_w, 32, W, DO_SIGNCOV) +VSIGNCOV(vsigncov_d, 64, D, DO_SIGNCOV) -- 2.31.1