Adds read-only field masks for the I3C device and controller registers.
Signed-off-by: Joe Komlodi <koml...@google.com>
Reviewed-by: Patrick Venture <vent...@google.com>
---
hw/i3c/aspeed_i3c.c | 56 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 034a17ff8e..6f514bef5e 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -330,6 +330,21 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2)
FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
+static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_DEVICE_NR_REGS] = {
+ [R_I3C1_REG0] = 0xfc000000,
+ [R_I3C1_REG1] = 0xfff00000,
+ [R_I3C2_REG0] = 0xfc000000,
+ [R_I3C2_REG1] = 0xfff00000,
+ [R_I3C3_REG0] = 0xfc000000,
+ [R_I3C3_REG1] = 0xfff00000,
+ [R_I3C4_REG0] = 0xfc000000,
+ [R_I3C4_REG1] = 0xfff00000,
+ [R_I3C5_REG0] = 0xfc000000,
+ [R_I3C5_REG1] = 0xfff00000,
+ [R_I3C6_REG0] = 0xfc000000,
+ [R_I3C6_REG1] = 0xfff00000,
+};
+
static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_HW_CAPABILITY] = 0x000e00bf,
[R_QUEUE_THLD_CTRL] = 0x01000101,
@@ -358,6 +373,45 @@ static const uint32_t
ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
[R_SLAVE_CONFIG] = 0x00000023,
};
+static const uint32_t ast2600_i3c_device_ro[ASPEED_I3C_DEVICE_NR_REGS] = {
+ [R_DEVICE_CTRL] = 0x04fffe00,
+ [R_DEVICE_ADDR] = 0x7f807f80,
+ [R_HW_CAPABILITY] = 0xffffffff,
+ [R_IBI_QUEUE_STATUS] = 0xffffffff,
+ [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8,
+ [R_IBI_QUEUE_CTRL] = 0xfffffff0,
+ [R_RESET_CTRL] = 0xffffffc0,
+ [R_SLV_EVENT_CTRL] = 0xffffff3f,
+ [R_INTR_STATUS] = 0xffff809f,
+ [R_INTR_STATUS_EN] = 0xffff8080,
+ [R_INTR_SIGNAL_EN] = 0xffff8080,
+ [R_INTR_FORCE] = 0xffff8000,
+ [R_QUEUE_STATUS_LEVEL] = 0xffffffff,
+ [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff,
+ [R_PRESENT_STATE] = 0xffffffff,
+ [R_CCC_DEVICE_STATUS] = 0xffffffff,
+ [R_I3C_VER_ID] = 0xffffffff,
+ [R_I3C_VER_TYPE] = 0xffffffff,
+ [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff,
+ [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff,
+ [R_SLV_PID_VALUE] = 0xffff0fff,
+ [R_SLV_CHAR_CTRL] = 0xffffffff,
+ [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff,
+ [R_SLV_MAX_LEN] = 0xffffffff,
+ [R_MAX_READ_TURNAROUND] = 0xffffffff,
+ [R_MAX_DATA_SPEED] = 0xffffffff,
+ [R_SLV_INTR_REQ] = 0xfffffff0,
+ [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0,
+ [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8,
+ [R_SCL_I3C_OD_TIMING] = 0xff00ff00,
+ [R_SCL_I3C_PP_TIMING] = 0xff00ff00,
+ [R_SCL_I2C_FMP_TIMING] = 0xff000000,
+ [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0,
+ [R_BUS_IDLE_TIMING] = 0xfff00000,
+ [R_EXTENDED_CAPABILITY] = 0xffffffff,
+ [R_SLAVE_CONFIG] = 0xffffffff,
+};
+
static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -387,6 +441,7 @@ static void aspeed_i3c_device_write(void *opaque, hwaddr
offset,
trace_aspeed_i3c_device_write(s->id, offset, value);
+ value &= ~ast2600_i3c_device_ro[addr];
switch (addr) {
case R_HW_CAPABILITY:
case R_RESPONSE_QUEUE_PORT:
@@ -475,6 +530,7 @@ static void aspeed_i3c_write(void *opaque,
addr >>= 2;
+ data &= ~ast2600_i3c_controller_ro[addr];
/* I3C controller register */
switch (addr) {
case R_I3C1_REG1:
--
2.40.0.348.gf938b09366-goog
