This patchset tries to fix some problem in current implementation for pointer mask, and add support for pointer mask of instruction fetch.
The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v6 v2: * drop some error patchs * Add patch 2 and 3 to fix the new problems * Add patch 4 and 5 to use PC-relative translation for pointer mask for instruction fetch v3: * use target_pc temp instead of cpu_pc to store into badaddr in patch 3 * use dest_gpr instead of tcg_temp_new() for succ_pc in patch 4 * enable CF_PCREL for system mode in seperate patch 5 v4： * Fix wrong pc_save value for conditional jump in patch 4 * Fix tcg_cflags overwrite problem to make CF_PCREL really work in new patch 5 * Fix tb mis-matched problem in new patch 6 v5: * use gen_get_target_pc to compute target address of auipc and successor address of jalr in patch 4. * separate tcg related fix patches(5, 6) from this patchset v6: * rename gen_get_target_pc as gen_pc_plus_diff in patch 3 and patch 4 * use gen_pc_plus_diff to compute successor address of jal in patch 4 * Mov comments for patch 5 to patch 4 Weiwei Li (6): target/riscv: Fix pointer mask transformation for vector address target/riscv: Update cur_pmmask/base when xl changes target/riscv: Fix target address to update badaddr target/riscv: Add support for PC-relative translation target/riscv: Enable PC-relative translation in system mode target/riscv: Add pointer mask support for instruction fetch target/riscv/cpu.c | 31 ++++++++---- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 20 +++++++- target/riscv/csr.c | 11 ++-- target/riscv/insn_trans/trans_rvi.c.inc | 37 ++++++++++---- target/riscv/translate.c | 67 ++++++++++++++++++------- target/riscv/vector_helper.c | 2 +- 7 files changed, 126 insertions(+), 43 deletions(-) -- 2.25.1
