v6: 20230325105429.1142530-1-richard.hender...@linaro.org Changes for v7: * Rebase on Alistair's riscv-to-apply.next. * Replace priv_level() with ctx->priv in trans_xthead.c.inc (Zhiwei).
r~ Fei Wu (2): target/riscv: Separate priv from mmu_idx target/riscv: Reduce overhead of MSTATUS_SUM change LIU Zhiwei (4): target/riscv: Extract virt enabled state from tb flags target/riscv: Add a general status enum for extensions target/riscv: Encode the FS and VS on a normal way for tb flags target/riscv: Add a tb flags field for vstart Richard Henderson (19): target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags accel/tcg: Add cpu_ld*_code_mmu target/riscv: Use cpu_ld*_code_mmu for HLVX target/riscv: Handle HLV, HSV via helpers target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT target/riscv: Introduce mmuidx_sum target/riscv: Introduce mmuidx_priv target/riscv: Introduce mmuidx_2stage target/riscv: Move hstatus.spvp check to check_access_hlsv target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index target/riscv: Check SUM in the correct register target/riscv: Hoist second stage mode change to callers target/riscv: Hoist pbmte and hade out of the level loop target/riscv: Move leaf pte processing out of level loop target/riscv: Suppress pte update with is_debug target/riscv: Don't modify SUM with is_debug target/riscv: Merge checks for reserved pte flags target/riscv: Reorg access check in get_physical_address target/riscv: Reorg sum check in get_physical_address include/exec/cpu_ldst.h | 9 + target/riscv/cpu.h | 47 +- target/riscv/cpu_bits.h | 12 +- target/riscv/helper.h | 12 +- target/riscv/internals.h | 35 ++ accel/tcg/cputlb.c | 48 +++ accel/tcg/user-exec.c | 58 +++ target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 403 +++++++++--------- target/riscv/csr.c | 21 +- target/riscv/op_helper.c | 113 ++++- target/riscv/translate.c | 70 +-- .../riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvf.c.inc | 2 +- target/riscv/insn_trans/trans_rvh.c.inc | 137 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 22 +- target/riscv/insn_trans/trans_xthead.c.inc | 14 +- 17 files changed, 591 insertions(+), 416 deletions(-) -- 2.34.1