On Fri, Apr 14, 2023 at 8:19 AM Philippe Mathieu-Daudé <phi...@linaro.org> wrote:
> Having this patch split in 2 (documentation first, logical change then) > would ease code review. > > > There is one functional change: > > > > Before this change, MOVNTPS and MOVNTPD were labeled as Exception Class > > 4 (only requiring alignment for legacy SSE instructions). This changes > > them to Exception Class 1 (always requiring memory alignment), as > > documented in the Intel manual. > > This could be a 3rd patch. > Apologies for the delayed response - I just noticed your reply today. I've split this into three separate patches as suggested ( https://lore.kernel.org/qemu-devel/20230501111428.95998-1-ri...@rzhou.org/T/), thanks! Ricky
