Hi there, This series enables Loongson-3A4000 TCG for system emulation. It Implemented Loongson CSR insertions which is required for Linux Kernel to probe CPU features and removed CPU type restrictions for loongson3_virt board.
This series is based on two of my previous series[1] [2]. However it's just a soft dependency for me to do boot test, feel free to apply this series without them. Note that loongarch_ipi is still not hooked up in IOCSR. I've sucessfully done it locally but I just want to confirm some details on hardware. Thanks - Jiaxun [1]: https://lore.kernel.org/qemu-devel/20230521102307.87081-1-jiaxun.y...@flygoat.com/T/#t [2]: https://lore.kernel.org/qemu-devel/0bb0cded-8450-536e-b90f-1a9d33311...@linaro.org/T/#t Jiaxun Yang (2): target/mips: Implement Loongson CSR instructions hw/mips/loongson3_virt: Remove CPU restrictions for TCG hw/mips/loongson3_virt.c | 4 -- target/mips/cpu-defs.c.inc | 9 ++++ target/mips/cpu.c | 8 ++++ target/mips/cpu.h | 40 ++++++++++++++++ target/mips/helper.h | 4 ++ target/mips/internal.h | 2 + target/mips/tcg/lcsr.decode | 17 +++++++ target/mips/tcg/lcsr_translate.c | 69 ++++++++++++++++++++++++++++ target/mips/tcg/meson.build | 2 + target/mips/tcg/op_helper.c | 16 +++++++ target/mips/tcg/sysemu/lcsr_helper.c | 45 ++++++++++++++++++ target/mips/tcg/sysemu/meson.build | 4 ++ target/mips/tcg/sysemu_helper.h.inc | 8 ++++ target/mips/tcg/translate.c | 3 ++ target/mips/tcg/translate.h | 7 +++ 15 files changed, 234 insertions(+), 4 deletions(-) create mode 100644 target/mips/tcg/lcsr.decode create mode 100644 target/mips/tcg/lcsr_translate.c create mode 100644 target/mips/tcg/sysemu/lcsr_helper.c -- 2.39.2 (Apple Git-143)
