Jonathan Cameron <jonathan.came...@huawei.com> writes:
> Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
> provides information related to DRAM devices.
>
> Example injection command in QMP:
>
> { "execute": "cxl-inject-dram-event",
> "arguments": {
> "path": "/machine/peripheral/cxl-mem0",
> "log": "informational",
> "flags": 1,
> "physaddr": 1000,
> "descriptor": 3,
> "type": 3,
> "transaction-type": 192,
> "channel": 3,
> "rank": 17,
> "nibble-mask": 37421234,
> "bank-group": 7,
> "bank": 11,
> "row": 2,
> "column": 77,
> "correction-mask": [33, 44, 55,66]
> }}
>
> Reviewed-by: Ira Weiny <ira.we...@intel.com>
> Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
[...]
> index 9dcd308a49..190db58385 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -55,6 +55,41 @@
> '*device': 'uint32', '*component-id': 'str'
> }}
>
> +##
> +# @cxl-inject-dram-event:
> +#
> +# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2)
> +# This event type is reported via one of the event logs specified via
> +# the log parameter.
> +#
> +# @path: CXL type 3 device canonical QOM path
> +# @log: Event Log to add the event to
> +# @flags: header flags
> +# @physaddr: Physical Address
> +# @descriptor: Descriptor
> +# @type: Type
> +# @transaction-type: Transaction Type
> +# @channel: Channel
> +# @rank: Rank
> +# @nibble-mask: Identify one or more nibbles that the error affects
> +# @bank-group: Bank group
> +# @bank: Bank
> +# @row: Row
> +# @column: Column
My comments on cxl-inject-gen-media-event's doc comment in the previous
patch apply.
> +# @correction-mask: Bits within each nibble. Used in order of bits set
> +# in the nibble-mask. Up to 4 nibbles may be covered.
> +#
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-dram-event',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> + 'physaddr': 'uint64', 'descriptor': 'uint8',
> + 'type': 'uint8', 'transaction-type': 'uint8',
> + '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> + '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> + '*column': 'uint16', '*correction-mask': [ 'uint64' ]
> + }}
> +
> ##
> # @cxl-inject-poison:
> #
Please format like
##
# @cxl-inject-dram-event:
#
# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2) This
# event type is reported via one of the event logs specified via the
# log parameter.
#
# @path: CXL type 3 device canonical QOM path
#
# @log: Event Log to add the event to
#
# @flags: header flags
#
# @physaddr: Physical Address
#
# @descriptor: Descriptor
#
# @type: Type
#
# @transaction-type: Transaction Type
#
# @channel: Channel
#
# @rank: Rank
#
# @nibble-mask: Identify one or more nibbles that the error affects
#
# @bank-group: Bank group
#
# @bank: Bank
#
# @row: Row
#
# @column: Column
#
# @correction-mask: Bits within each nibble. Used in order of bits
# set in the nibble-mask. Up to 4 nibbles may be covered.
#
# Since: 8.1
##
to blend in with recent commit a937b6aa739 (qapi: Reformat doc comments
to conform to current conventions).
