> -----Original Message-----
> From: Marco Liebel (QUIC) <quic_mlie...@quicinc.com>
> Sent: Monday, May 22, 2023 11:14 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson <tsimp...@quicinc.com>; Brian Cain
> <bc...@quicinc.com>; Marco Liebel (QUIC) <quic_mlie...@quicinc.com>
> Subject: [PATCH] Hexagon (target/hexagon) Fix assignment to tmp registers
>
> The order in which instructions are generated by gen_insn() influences
> assignment to tmp registers. During generation, tmp instructions (e.g.
> generate_V6_vassign_tmp) use vreg_src_off() to determine what kind of
> register to use as source. If some instruction (e.g.
> generate_V6_vmpyowh_64_acc) uses a tmp register but is generated prior to
> the corresponding tmp instruction, the vregs_updated_tmp bit map isn't
> updated in time.
>
> Exmple:
> { v14.tmp = v16; v25 = v14 } This works properly because
> generate_V6_assign_tmp is generated before generate_V6_assign and
> the bit map is updated.
>
> { v15:14.tmp = vcombine(v21, v16); v25:24 += vmpyo(v18.w,v14.h) }
> This does not work properly because vmpyo is generated before
> vcombine and therefore the bit map does not yet know that there's
> a tmp register.
>
> The parentheses in the decoding function were in the wrong place.
> Moving them to the correct location makes shuffling of .tmp vector registers
> work as expected.
> ---
> target/hexagon/mmvec/decode_ext_mmvec.c | 6 ++---
> tests/tcg/hexagon/hvx_misc.c | 31 +++++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 3 deletions(-)
Two things
1) Update the copyright year in decode_ext_mmvec.c
2) Add your Signed-off-by to the commit message
Otherwise,
Tested-by: Taylor Simpson <tsimp...@quicinc.com>
Reviewed-by: Taylor Simpson <tsimp...@quicinc.com>
Queued for next Hexagon update
