On 23/5/23 13:18, Jiaxun Yang wrote:
2023年5月23日 11:01，Song Gao <gaos...@loongson.cn> 写道：
在 2023/5/23 上午11:22, Jiaxun Yang 写道:
[...]
Is totally the same on MIPS and LoongArch. I’m guarding them out because
We have different way to get IOCSR address space on MIPS, which is due
to be implemented.
I can further abstract out a function to get IOCSR address space. But still,
I think the best way to differ those two architecture is using TARGET_* macros,
as it doesn’t make much sense to have unused code for another architecture
compiled.
Most of the code in hw/intc or hw/ uses property to distinguish between
different devices, not TARGE_* macro.
They are the *same* device, with different way to handle IOCSR address space.
Another problem is casting CPUState with LOONGARCH_CPU() is something invalid on
MIPS, vice-versa. We are potentially introducing a security issue here.
I know nobody have done something like this before, but not necessarily to be a
bad idea.
I’ll introduce something like:
+#ifdef TARGET_LOONGARCH64
+static inline void *AddressSpace get_iocsr_as(int cpuid)
+{
+ CPUState *cs = qemu_get_cpu(cpuid);
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+
+ return &cpu->env.address_space_iocsr;
+}
+#endif
+
+#ifdef TARGET_MIPS64
+static inline void *AddressSpace get_iocsr_as(int cpuid)
+{
+ CPUState *cs = qemu_get_cpu(cpuid);
+ MIPSCPU *cpu = MIPS_CPU(cs);
+
+ return &cpu->env.iocsr.as;
+}
+#endif
Introduce a QOM interface that provides a get_iocsr_as() implementation.
See for example how TYPE_IDAU_INTERFACE works.
