On Tue, May 23, 2023 at 7:38 PM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> Pass RISCVCPUConfig as disassemble_info.target_info to support disas
> of conflict instructions related to specific extensions.
>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> disas/riscv.c | 10 +++++++---
> target/riscv/cpu.c | 1 +
> 2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e61bda5674..729ab684da 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -19,7 +19,7 @@
>
> #include "qemu/osdep.h"
> #include "disas/dis-asm.h"
> -
> +#include "target/riscv/cpu_cfg.h"
>
> /* types */
>
> @@ -967,6 +967,7 @@ typedef enum {
> /* structures */
>
> typedef struct {
> + RISCVCPUConfig *cfg;
> uint64_t pc;
> uint64_t inst;
> int32_t imm;
> @@ -4855,11 +4856,13 @@ static void decode_inst_decompress(rv_decode *dec,
> rv_isa isa)
> /* disassemble instruction */
>
> static void
> -disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
> +disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
> + RISCVCPUConfig *cfg)
> {
> rv_decode dec = { 0 };
> dec.pc = pc;
> dec.inst = inst;
> + dec.cfg = cfg;
> decode_inst_opcode(&dec, isa);
> decode_inst_operands(&dec, isa);
> decode_inst_decompress(&dec, isa);
> @@ -4914,7 +4917,8 @@ print_insn_riscv(bfd_vma memaddr, struct
> disassemble_info *info, rv_isa isa)
> break;
> }
>
> - disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
> + disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
> + (RISCVCPUConfig *)info->target_info);
> (*info->fprintf_func)(info->stream, "%s", buf);
>
> return len;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db0875fb43..4fe926cdd1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -818,6 +818,7 @@ static void riscv_cpu_reset_hold(Object *obj)
> static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> {
> RISCVCPU *cpu = RISCV_CPU(s);
> + info->target_info = &cpu->cfg;
>
> switch (riscv_cpu_mxl(&cpu->env)) {
> case MXL_RV32:
> --
> 2.25.1
>
>
