On 09.02.2012, at 08:43, Thomas Huth wrote: > Am Thu, 9 Feb 2012 11:26:09 +1100 > schrieb David Gibson <d...@au1.ibm.com>: > >> On Wed, Feb 08, 2012 at 02:27:35PM +0100, Thomas Huth wrote: >>> Am Wed, 8 Feb 2012 21:48:40 +1100 >>> schrieb David Gibson <da...@gibson.dropbear.id.au>: >>> >>>> On Wed, Feb 08, 2012 at 10:54:21AM +0400, malc wrote: >>>>> On Wed, 8 Feb 2012, David Gibson wrote: >>>>> >>>>>> From: Thomas Huth <th...@linux.vnet.ibm.com> >>>>>> >>>>>> These instructions for loading and storing byte-swapped 64-bit values >>>>>> have >>>>>> been introduced in PowerISA 2.06. >>>>>> >>>>>> Signed-off-by: Thomas Huth <th...@linux.vnet.ibm.com> >>>>>> --- >>>>>> target-ppc/translate.c | 30 ++++++++++++++++++++++++++++++ >>>>>> 1 files changed, 30 insertions(+), 0 deletions(-) >>>>> >>>>> I seem to recall that POWER5 machine i had access to didn't have >>>>> ld/stdbrx while CBE did have it (or was it the other way around?) >>>>> so question is - is PPC_64B sufficient? >>>> >>>> Ah, I think it's not. I think I spotted that before, but then forgot >>>> about it. Thanks for the reminder. >>> >>> Maybe it's a better idea to use PPC_64BX here? ... but that flag seems >>> to be missing in POWERPC_INSNS_POWER7... David, could PPC_64BX also be >>> included in that flag list? >> >> Um.. what exactly do you mean by 64BX? >> > > There is a definition in target-ppc/cpu.h: > > /* New 64 bits extensions (PowerPC 2.0x) */ > PPC_64BX = 0x0000000000000040ULL, > > According to the comment, I thought the PPC_64BX might be designed > for new 64-bit instructions?
Well, we need to be a bit more specific here to know what we're implementing. The flag above just indicates the lq opcode: target-ppc/translate.c:GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), So how about we create a new PPC2 flag for BRX and add that in POWER7 INSNS? If you could find out if Cell also supports these instructions, that'd be great. I don't have a 2.05 spec handy and 2.04 doesn't implement it yet. Alex