This patch adds the new syscall for the "RISC-V Hardware Probing Interface" (https://docs.kernel.org/riscv/hwprobe.html).
Signed-off-by: Robbin Ehn <r...@rivosinc.com> --- linux-headers/asm-riscv/unistd.h | 9 +++ linux-user/riscv/cpu_loop.c | 119 ++++++++++++++++++++++++++++++- linux-user/riscv/syscall32_nr.h | 1 + linux-user/riscv/syscall64_nr.h | 1 + 4 files changed, 129 insertions(+), 1 deletion(-) diff --git a/linux-headers/asm-riscv/unistd.h b/linux-headers/asm-riscv/unistd.h index 73d7cdd2ec..950ab3fd44 100644 --- a/linux-headers/asm-riscv/unistd.h +++ b/linux-headers/asm-riscv/unistd.h @@ -43,3 +43,12 @@ #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) #endif __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) + +/* + * Allows userspace to query the kernel for CPU architecture and + * microarchitecture details across a given set of CPUs. + */ +#ifndef __NR_riscv_hwprobe +#define __NR_riscv_hwprobe (__NR_arch_specific_syscall + 14) +#endif +__SYSCALL(__NR_riscv_hwprobe, sys_riscv_hwprobe) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index bffca7db12..5207739185 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -26,6 +26,117 @@ #include "elf.h" #include "semihosting/common-semi.h" +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 + +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) + +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) + +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) + +struct riscv_hwprobe { + int64_t key; + uint64_t value; +}; + +static void hwprobe_one_pair(CPURISCVState *env, struct riscv_hwprobe *pair) +{ + const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); + + pair->value = 0; + + switch (pair->key) { + case RISCV_HWPROBE_KEY_MVENDORID: + pair->value = cfg->mvendorid; + break; + case RISCV_HWPROBE_KEY_MARCHID: + pair->value = cfg->marchid; + break; + case RISCV_HWPROBE_KEY_MIMPID: + pair->value = cfg->mimpid; + break; + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + pair->value = riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) ? + RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0; + break; + case RISCV_HWPROBE_KEY_IMA_EXT_0: + pair->value = riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) ? + RISCV_HWPROBE_IMA_FD : 0; + pair->value |= riscv_has_ext(env, RVC) ? + RISCV_HWPROBE_IMA_C : pair->value; + break; + case RISCV_HWPROBE_KEY_CPUPERF_0: + pair->value = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + break; + default: + pair->key = -1; + break; + } +} + +static long sys_riscv_hwprobe(CPURISCVState *env, + abi_ulong user_pairs, + size_t pair_count, + size_t cpu_count, + abi_ulong user_cpus, + unsigned int flags) +{ + struct riscv_hwprobe *host_pairs; + cpu_set_t *host_cpus = NULL; + size_t cpu_setsize = 0; + + /* flags must be 0 */ + if (flags != 0) { + return 1 + }; + + /* inconsistence cpu_set */ + if (cpu_count != 0 && user_cpus == 0) { + return 1; + } + + host_pairs = lock_user(VERIFY_WRITE, user_pairs, + sizeof(*host_pairs) * pair_count, 0); + + if (host_pairs == NULL) { + return 1; + } + + if (user_cpus != 0) { + cpu_setsize = CPU_ALLOC_SIZE(user_cpus); + host_cpus = lock_user(VERIFY_READ, user_cpus, cpu_setsize, 0); + } + + /* cpuset is ignored, symmetric CPUs in qemu */ + + for (struct riscv_hwprobe *ipairs = host_pairs; + pair_count > 0; + pair_count--, ipairs++) { + hwprobe_one_pair(env, ipairs); + } + + if (host_cpus != 0) { + unlock_user(host_cpus, user_cpus, cpu_setsize); + } + + unlock_user(host_pairs, user_pairs, sizeof(*host_pairs) * pair_count); + return 0; +}; + void cpu_loop(CPURISCVState *env) { CPUState *cs = env_cpu(env); @@ -47,7 +158,13 @@ void cpu_loop(CPURISCVState *env) break; case RISCV_EXCP_U_ECALL: env->pc += 4; - if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) { + if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 14) { + /* riscv_hwprobe */ + ret = sys_riscv_hwprobe(env, + env->gpr[xA0], env->gpr[xA1], + env->gpr[xA2], env->gpr[xA3], + env->gpr[xA4]); + } else if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) { /* riscv_flush_icache_syscall is a no-op in QEMU as self-modifying code is automatically detected */ ret = 0; diff --git a/linux-user/riscv/syscall32_nr.h b/linux-user/riscv/syscall32_nr.h index 1327d7dffa..412e58e5b2 100644 --- a/linux-user/riscv/syscall32_nr.h +++ b/linux-user/riscv/syscall32_nr.h @@ -228,6 +228,7 @@ #define TARGET_NR_accept4 242 #define TARGET_NR_arch_specific_syscall 244 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) #define TARGET_NR_prlimit64 261 #define TARGET_NR_fanotify_init 262 #define TARGET_NR_fanotify_mark 263 diff --git a/linux-user/riscv/syscall64_nr.h b/linux-user/riscv/syscall64_nr.h index 6659751933..29e1eb2075 100644 --- a/linux-user/riscv/syscall64_nr.h +++ b/linux-user/riscv/syscall64_nr.h @@ -251,6 +251,7 @@ #define TARGET_NR_recvmmsg 243 #define TARGET_NR_arch_specific_syscall 244 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) #define TARGET_NR_wait4 260 #define TARGET_NR_prlimit64 261 #define TARGET_NR_fanotify_init 262 -- 2.39.2